DETAILED ACTION
Claims 1, 8, 9, 10, 17 and 18 have been amended. Claims 2 and 11 have been cancelled. Claims 1, 3-10 and 12-18 remain pending in the application.
Claims 1 and 10 are independent.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This action is final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment and Arguments
Applicant’s amendments to the Specification and Claims have overcome each and every objection and 112(b) and 101 rejections previously set forth in the Non-Final Office Action. As a result, each and every objection and 112(b) and 101 rejections have been withdrawn.
Applicant's arguments regarding 35 USC § 102/103 rejections with respect to amended claims have been fully considered but in moot in view of new ground of rejection.
Applicant amended independent claims to further specify:
a tracking information graphics unit, configured to generate a wafer movement tracking graph according to the machine action events that have been bound to the account point information, wherein in the wafer movement tracking graph, a plurality of horizontal bars are used to illustrate the machine action events over time,
wherein the operation interface comprises an original record window, a condition window and an event window; the original record window is configured to display the semiconductor machine log file, the condition window is configured to set at least one search condition, and the event window is configured to display the machine action events.
TAKANO US 20090142168 A1 is introduced in response to amended claims. The teachings of YANG, MOCHIZUKI, YANG KAI-TING and RHEE as disclosed in the previous office action are hereby incorporated by references to the extent applicable to the amended claims.
Applicant’s other arguments were directed to certain features are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Another iteration of claim analysis has been made. Referring to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over YANG CN 108363361 B in view of TAKANO US 20090142168 A1 and MOCHIZUKI JP 2008140248 A1.
Regarding claim 1, YANG teaches an analysis method of a semiconductor manufacturing process (Figs. 1 &2 page 3 paragraphs 1 & 5), a machine operation flow dynamic display system), comprising:
loading a semiconductor machine log file (Fig. 2, page 3 paragraph 6, retrieves the log);
defining a plurality of machine action events from the semiconductor manufacturing machine log file (Fig. 2, page 3 paragraphs 7-9, log record is analyzed and interpreted to obtain operation items and associated time);
generating a wafer moving path map according to a wafer moving information file (Fig. 4, page 3 paragraph 2 to page 4 paragraph 2, the map editing module retrieves graphic file 50 of the machine i.e “a wafer moving information file”, and makes the processing time and operation items in the obtained operation items and associated time file correspond to the relative arrangement of the operation unit in the graphic file i.e. “generating a wafer moving path map according to a wafer moving information file”);
binding a plurality of account point information to each of the machine action events according to the wafer moving path map (Figs. 6, 7A & 7B, page 4 paragraphs 3- 6, the chamber name, wafer ID and batch ID etc. are bound to each of the operation items); and
generating a wafer movement tracking graph according to the machine action events that have been bound to the account point information (Figs. 7A & 7B and 8, page 4 paragraphs 5-6 and page 5 paragraph 3, an animation file is generated to present individual operational items during the operational period);
wherein in the step of defining the machine action events, an operation interface comprises a condition window and an event window, the condition window is configured to set at least one search condition, and the event window is configured to display the machine action events (page 3 paragraph 7, log parsing module searches relevant operation items using keyword, page 4 paragraph 6, display area 72 wafer number is selected and operation state related to the selected wafer is displayed in display area 71 and 72).
YANG does not explicitly further teach:
in the wafer movement tracking graph, a plurality of horizontal bars are used to illustrate the machine action events over time; and
the operation interface comprises an original record window, the original record window is configured to display the semiconductor machine log file.
TAKANO explicitly teaches in an analogous art that in the wafer movement tracking graph, a plurality of horizontal bars are used to illustrate the machine action events over time (Fig. 8 [0164] – [0170] the machine action events over time are displayed using horizontal bars), and
MOCHIZUKI explicitly teaches in an analogous art that the operation interface comprises an original record window, the original record window is configured to display the semiconductor machine log file (Figs. 6, 11 and 15-16, page 7 paragraph 4 and page 8 paragraph 3, keywords are set in a keyword setting screen for searching log file, page 9 paragraph 2 log file is displayed on the log display field 442).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG to incorporate the teachings of TAKANO and MOCHIZUKI, because they all directed to wafer processing, to make the method wherein in the wafer movement tracking graph, a plurality of horizontal bars are used to illustrate the machine action events over time; and the operation interface comprises an original record window, the original record window is configured to display the semiconductor machine log file. One of ordinary skill in the art would have been motivated to do this modification so as to search the relevant object in log, as YANG teaches in page 3 paragraph 7, and analyze the standby time, as TAKANO teaches in [0170].
Regarding claim 6, YANG further teaches the wafer movement tracking graph corresponds to a wafer (Figs. 6, 7A & 7B, page 4 paragraphs 3- 6, corresponding to wafer ID).
Regarding claim 7, YANG further teaches the wafer movement tracking graph corresponds to a plurality of wafers (Figs. 6, 7A & 7B, page 4 paragraphs 3- 6, corresponding to batches).
Regarding claim 8, YANG in view of TAKANO further teaches a wait time is analyzed via the wafer movement tracking graph (Fig. 8 [0170] standby time is analyzed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG to incorporate the teachings of TAKANO, because they all directed to wafer processing, to make the method wherein a wait time is analyzed via the wafer movement tracking graph. One of ordinary skill in the art would have been motivated to do this modification so as to reduce the cycle time, as TAKANO teaches in [0014].
Regarding claim 9, YANG further teaches a time-consuming action is analyzed via the wafer movement tracking graph is configured to analyze a critical time-consuming action (page 3 paragraph 3 and page 4 paragraph 4 from the bottom, determine the time taken in individual operating items and analyze the time delay).
Regarding claim 10, it is directed to a device of carrying out the method with similar limitations as set forth in claim 1. Since YANG, TAKANO and MOCHIZUKI teach the claimed method, they teach the method device for implementing the method steps.
In addition, YANG further teaches an analysis device of a semiconductor manufacturing process comprises microprocess to carry out the method steps (Fig. 1 page 5 paragraph 3, a computer to perform the method steps); and
MOCHIZUKI further teaches an action definition unit, configured to provide an operation interface to define a plurality of machine action events from the semiconductor manufacturing machine log file (Figs. 6, 11 and 15-16, page 7 paragraph 4 and page 8 paragraph 3, keywords are set in a keyword setting screen for searching log file, page 9 paragraph 2 log file is displayed on the log display field 442).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG to incorporate the teachings of MOCHIZUKI, because they all directed to wafer processing, to make the device wherein an action definition unit, configured to provide an operation interface to define a plurality of machine action events from the semiconductor manufacturing machine log file. One of ordinary skill in the art would have been motivated to do this modification so as to search the relevant object in log, as YANG teaches in page 3 paragraph 7.
Regarding claims 15-18, they are directed to a device of carrying out the method with similar limitations as set forth in claims 6-9, respectively. Since YANG, TAKANO and MOCHIZUKI teach the claimed method, they teach the method device for implementing the method steps, respectively.
Claims 3-4 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over YANG in view of TAKANO and MOCHIZUKI as applied to claims 1, 6-10 and 15-18 above, further in view of YANG KAI-TING US 20220057775 A12.
Regarding claims 3 and 12, the combination of YANG, TAKANO and MOCHIZUKI does not explicitly further teach the wafer moving path map comprises a plurality of mechanism nodes and a plurality of paths connecting the mechanism nodes.
YANG KAI-TING explicitly teaches in an analogous art that the wafer moving path map comprises a plurality of mechanism nodes and a plurality of paths connecting the mechanism nodes (Fig. 3B [0034] the wafer moving path map with circles i.e. “mechanism nodes” and arrows i.e. “paths connecting the mechanism nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG, TAKANO and MOCHIZUKI to incorporate the teachings of YANG KAI-TING, because they all directed to wafer processing, to make the method wherein the wafer moving path map comprises a plurality of mechanism nodes and a plurality of paths connecting the mechanism nodes. One of ordinary skill in the art would have been motivated to do this modification so as to construct a model of wafer transfer sequence, as YANG KAI-TING teaches [0030].
Regarding claims 4 and 13, YANG in view of YANG KAI-TING further teaches the wafer moving path map is a closed path graph (Fig. 3B, tier 1, the wafer moving path map is a closed path graph).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG, TAKANO and MOCHIZUKI to incorporate the teachings of YANG KAI-TING, because they all directed to wafer processing, to make the method wherein the wafer moving path map is a closed path graph. One of ordinary skill in the art would have been motivated to do this modification so as to construct a model of wafer transfer sequence, as YANG KAI-TING teaches [0030].
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over YANG in view of TAKANO and MOCHIZUKI as applied to claims 1, 6-10 and 15-18 above, further in view of RHEE WO 2021237147 A13.
Regarding claims 5 and 14, YANG further teaches the account point information comprises a lot information (Figs. 7A & 7B page 4 paragraph 6, batch ID), a chamber information (Figs. 7A & 7B page 4 paragraph 6, chamber ID), a chamber program information (Fig. 6 table 30 second column, page 4 paragraph 5, the function name performed in respective chamber).
The combination of YANG, TAKANO and MOCHIZUKI does not explicitly further teach the account point information comprises a program name, a site information and a step information.
RHEE explicitly teaches in an analogous art that the account point information comprises a program name ([0040] recipe identifier), a site information ([0040] manufacturing tool) and a step information ([0040] sequence identifier).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YANG, TAKANO and MOCHIZUKI to incorporate the teachings of RHEE, because they all directed to wafer processing, to make the method wherein the account point information comprises a program name, a site information and a step information. One of ordinary skill in the art would have been motivated to do this modification so as to model the manufacturing tool, as RHEE teaches in [0041].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
TAKANO US 20080019809 A1 teaches substrate event time chart using horizontal bars.
TAKANO US 20070176265 A1 teaches substrate event time chart using horizontal bars.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael Tang whose telephone number is (571)272-7437. The examiner can normally be reached M-F 7:30-4 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached on (571)272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.T./Examiner, Art Unit 2115
/KAMINI S SHAH/Supervisory Patent Examiner, Art Unit 2115
1 YANG and MOCHIZUKI are the prior arts of record
2 YANG KAI-TING is the prior art of record
3 RHEE is the prior art of record
Prosecution Insights