The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MAENG et al. (U.S. Patent Application Publication 2021/0359100, hereinafter referred to as MAENG).
As to claim 1, MAENG teaches 1. A semiconductor memory device, comprising: an upper electrode; a lower electrode; an anti-ferroelectric layer disposed between the upper electrode and the lower electrode and comprising an anti-ferroelectric; an oxide layer disposed on a first surface of the anti-ferroelectric layer and comprising a high dielectric material; and a metal oxide layer disposed on a second surface of the anti-ferroelectric layer opposite to the first surface, wherein a thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the anti-ferroelectric layer. [see 101, 102, 431, 432, 421 in Fig. 8B for example]
As to claim 2, MAENG teaches 2. The semiconductor memory device of claim 1, further comprising: a ferroelectric layer disposed between the anti-ferroelectric layer and the oxide layer or between the anti-ferroelectric layer and the metal oxide layer, wherein the ferroelectric layer comprises a ferroelectric. [see 423, 423’, 421, 422 in Fig. 8B for example]
As to claim 3, MAENG teaches 3. The semiconductor memory device of claim 2, wherein the thickness of the anti-ferroelectric layer is greater than a thickness of the ferroelectric layer. [see 423, 423’, 421, 422 in Fig. 8B for example]
As to claim 4, MAENG teaches 4. The semiconductor memory device of claim 1, wherein the oxide layer is in contact with the first surface of the anti-ferroelectric layer, and the metal oxide layer is in contact with the second surface of the anti-ferroelectric layer. [see 331, 332, 320 in Fig. 5 for example]
As to claim 5, MAENG teaches 5. The semiconductor memory device of claim 1, wherein the anti-ferroelectric comprises at least one of ZrO2, PbZrO3, AgNbO3, or HfxZr1-xO2, wherein x is a positive number smaller than about 0.5. [¶0088]
As to claim 7, MAENG teaches 7. The semiconductor memory device of claim 1, wherein the high dielectric material comprises at least one of La2O3, Y2O3, Ta2O5, SrO, or Ga2O3. [¶0084]
As to claim 8, MAENG teaches 8. The semiconductor memory device of claim 1, wherein the metal oxide layer comprises at least one of Ta+5, W+6, Nb+5, Mo+6, In+3, Zn+2, Ga+3, or Ni+2. [¶0107]
As to claim 9, MAENG teaches 9. The semiconductor memory device of claim 1, wherein the high dielectric material has a bandgap energy of about 4.0 eV or more and about 6.0 eV or less, and has a dielectric constant of about 10 or more. [¶0084]
As to claim 10, MAENG teaches 10. The semiconductor memory device of claim 1, wherein the upper electrode is in contact with the oxide layer, the lower electrode is in contact with the metal oxide layer, and the anti-ferroelectric layer is in contact with at least one of the oxide layer or the metal oxide layer. [see Fig. 5 for example]
As to claim 11, MAENG teaches 11. A semiconductor memory device, comprising: an upper electrode; a lower electrode; a dielectric structure disposed between the upper electrode and the lower electrode; an oxide layer disposed between the lower electrode and the dielectric structure and comprising a high dielectric material; and a metal oxide layer disposed between the upper electrode and the dielectric structure and comprising a metal material, wherein the dielectric structure comprises at least one anti-ferroelectric layer comprising an anti-ferroelectric, a thickness of each of the oxide layer and the metal oxide layer in a direction orthogonal to an upper surface of the upper electrode is less than a thickness of the dielectric structure, and the oxide layer is in contact with the lower electrode, and the metal oxide layer is in contact with the upper electrode. [see 101, 102, 431, 432, 421 in Fig. 8B for example]
As to claim 12, MAENG teaches 12. The semiconductor memory device of claim 11, wherein the at least one anti-ferroelectric layer is one of a plurality of anti-ferroelectric layers, the dielectric structure further comprises a plurality of ferroelectric layers comprising a plurality of ferroelectrics, and the anti-ferroelectric layer and the ferroelectric layer are alternately laminated between the oxide layer and the metal oxide layer. [see 101, 102, 431, 432, 421 in Fig. 8B for example]
As to claim 13, MAENG teaches 13. The semiconductor memory device of claim 12, wherein a ferroelectric layer disposed closest to the oxide layer among the plurality of ferroelectric layers is disposed closer to the oxide layer than an anti-ferroelectric layer that is disposed closest to the oxide layer among the plurality of anti-ferroelectric layers. [see Fig. 8B for example]
As to claim 14, MAENG teaches 14. The semiconductor memory device of claim 11, wherein the anti-ferroelectric comprises at least one of ZrO2, PbZrO3, AgNbO3, or HfxZr1-xO2, wherein x is a positive number smaller than 0.5. [¶0088]
As to claim 15, MAENG teaches 15. The semiconductor memory device of claim 12, wherein thicknesses of the plurality of anti-ferroelectric layers are different from each other, and thicknesses of the plurality of ferroelectric layers are different from each other. [see Fig. 8B for example]
As to claim 17, MAENG teaches 17. The semiconductor memory device of claim 11, wherein the high dielectric material comprises at least one of La2O3, Y2O3, Ta2O5, SrO, or Ga2O3. [¶0084]
As to claim 18, MAENG teaches 18. The semiconductor memory device of claim 11, wherein the metal material comprises at least one of Ta+5, W+6, Nb+5, Mo+6, In+3, Zn+2, Ga+3, or Ni+2. [¶0107]
As to claim 19, MAENG teaches 19. A semiconductor memory device, comprising: a substrate; an active region defined by a device separation layer formed on the substrate; a word line crossing the active region and extending in a first direction on the substrate; a bit line extending in a second direction orthogonal to the first direction on the substrate; and a capacitor disposed at a higher level than the bit line, wherein the capacitor comprises: at least one anti-ferroelectric layer comprising an upper electrode, a lower electrode, and an anti-ferroelectric disposed between the upper electrode and the lower electrode; an oxide layer disposed between the upper electrode and the anti-ferroelectric layer and comprising a high dielectric material; and a metal oxide layer disposed between the lower electrode and the anti-ferroelectric layer and comprising a metal material, wherein a thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the at least one anti-ferroelectric layer. [¶0117; see rejection claim 1 above]
As to claim 20, MAENG teaches 20. The semiconductor memory device of claim 19, further comprising: a plurality of ferroelectric layers comprising ferroelectrics, wherein the at least one anti-ferroelectric layer is one of a plurality of anti-ferroelectric layers, and the anti-ferroelectric layers and the ferroelectric layers are alternately laminated between the oxide layer and the metal oxide layer. [see Fig. 8 for example]
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 6, 16 rejected under 35 U.S.C. 103(a) as being unpatentable over MAENG.
As to claim 6, MAENG may not explicitly teach 6. The semiconductor memory device of claim 1, wherein a vertical distance between the oxide layer and the metal oxide layer is about 5 Å or more and less than about 100 Å.
The Examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was made to come up with the disclosed dimension of the structure.
As to claim 16, MAENG may not explicitly teach 16. The semiconductor memory device of claim 11, wherein a thickness of the at least one anti-ferroelectric layer is about 5 Å or more and about 95 Å or less.
The Examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was made to come up with the disclosed dimension of the structure.
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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