The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 13-15, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (U.S. Patent Application Publication 2024/0046861, hereinafter referred to as Wang).
As to claim 1, Wang teaches 1. An array substrate, comprising a substrate, a semiconductor layer over the substrate, a gate over a side of the semiconductor layer away from the substrate, and a source and a drain on sides of the gate, wherein the semiconductor layer comprises a channel region, a first doping region, and a first ohmic contact region, which are sequentially connected; and a shielding layer between the substrate and the semiconductor layer, wherein the shielding layer is connected to a fixed potential, and the shielding layer at least partially overlaps with the first doping region in a direction perpendicular to a plane of the substrate. [see 20, 51 in Fig. 3A for example; ¶0085]
As to claim 2, Wang teaches 2. The array substrate according to claim 1, wherein a first junction is a junction of the first doping region and the channel region, a second junction is a junction of the first doping region and the first ohmic contact region, and the shielding layer cover the first junction and/or second junction in the direction perpendicular to the plane of the substrate. [see 211, 212, 213, and 51 in Fig. 3A for example; ¶0085]
As to claim 13, Wang teaches 13. The array substrate according to claim 1, wherein the first ohmic contact region is electrically connected to the drain. [see 23, 211 in Fig3B]
As to claim 14, Wang teaches 14. The array substrate according to claim 1, wherein the semiconductor layer further comprises a second doping region and a second ohmic contact region over a side of the channel away from the first doping region, and the second ohmic contact region is electrically connected to the source. [see 23, 212 in Fig3B]
As to claim 15, Wang teaches 15. The array substrate according to claim 14, wherein along the direction from the channel region to the first ohmic contact region, a length of the first doping region is D1, and along the direction from the second ohmic contact region to the channel region, a length of the second doping region is D2, wherein D1＞D2. [see 23, 211, 212 in Fig3B]
As to claim 18, Wang teaches 18. The array substrate according to claim 1, wherein the array substrate comprises a plurality of first signal lines, the first signal line is on the same layer as the source and the drain, and the first signal line is electrically connected to the shielding layer. [¶0020]
As to claim 19, Wang teaches 19. A display panel comprising: an array substrate, comprising: a substrate, a semiconductor layer over the substrate, a gate over a side of the semiconductor layer away from the substrate, and a source and a drain on sides of the gate, wherein the semiconductor layer comprises a channel region, a first doping region, and a first ohmic contact region, which are sequentially connected; and a shielding layer between the substrate and the semiconductor layer, wherein the shielding layer is connected to a fixed potential, and the shielding layer at least partially overlaps with the first doping region in a direction perpendicular to a plane of the substrate. [see 20, 51 in Fig. 3A for example; ¶0085]
As to claim 20, Wang teaches 20. The display panel according to claim 19, wherein a first junction is a junction of the first doping region and the channel region, a second junction is a junction of the first doping region and the first ohmic contact region, and the shielding layer cover the first junction and/or second junction in the direction perpendicular to the plane of the substrate. [see 20, 51 in Fig. 3A for example; ¶0085]
Allowable Subject Matter
Claims 3-12, 16-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Claims 1-2, 13-15, 18-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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