The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YASUHIRO et al. (JP2011041179, IDS, hereinafter referred to as YASUHIRO).
As to claim 1, YASUHIRO teaches 1. A semiconductor device comprising: a transistor; and a plurality of metal layers that is respectively arranged in a plurality of layers stacked above the transistor, wherein the plurality of metal layers includes: a first metal layer that is arranged in a lowermost layer of the plurality of layers; a second metal layer that is arranged in an uppermost layer of the plurality of layers and that is thicker than the first metal layer; and a third metal layer that is arranged in the uppermost layer and that is thicker than the second metal layer. [117, 125, 105, 115, 123 Figs. 1, 5; ¶0050, 0052~0053, 0063~0064]
As to claim 2, YASUHIRO teaches 2. The semiconductor device according to claim 1, wherein the third metal layer has a thickness 40 times or more a thickness of the first metal layer. [¶0058]
As to claim 3, YASUHIRO teaches 3. The semiconductor device according to claim 1, wherein the third metal layer has a round shape with an outer edge portion rounded. [¶0027, 0030]
As to claim 4, YASUHIRO teaches 4. The semiconductor device according to claim 1, further comprising an insulating layer that is arranged in the uppermost layer and has an opening portion, wherein the second metal layer is covered with the insulating layer, and the third metal layer has an upper surface exposed from the opening portion. [108 Fig.5]
As to claim 5, YASUHIRO teaches 5. The semiconductor device according to claim 4, wherein the third metal layer includes: a first layer that includes a first metal; a second layer that includes a metal different from the first metal and is arranged below the first layer; and a third layer that includes a second metal different from the first metal and is arranged above the first layer. [Fig.5]
As to claim 6, YASUHIRO teaches 6. The semiconductor device according to claim 5, wherein the second metal layer includes: the first layer; and the second layer, and the third layer is selectively arranged on the first layer of the third metal layer of the second and third metal layers. [Fig.5]
As to claim 7, YASUHIRO teaches 7. The semiconductor device according to claim 4, wherein at least part of a metal layer arranged in a layer below the uppermost layer of the plurality of metal layers is electrically connected to the transistor, the second metal layer is a re-distribution layer that changes a wiring drawn position of the at least part of the metal layer, and the third metal layer is an electrode pad that is connectable to an external device. [Fig.5]
As to claim 8, YASUHIRO teaches 8. The semiconductor device according to claim 1, wherein the third metal layer is arranged on a layer below the uppermost layer, and the second metal layer is arranged above the layer below without making contact with the layer below. [Fig.5]
As to claim 9, YASUHIRO teaches 9. The semiconductor device according to claim 8, wherein the third metal layer includes: a first layer that includes a first metal; and a second layer that includes a metal different from the first metal and is arranged below the first layer. [Fig.5]
As to claim 10, YASUHIRO teaches 10. The semiconductor device according to claim 9, wherein the second metal layer includes a second metal that is different from the first metal, and the third metal layer further includes a third layer that includes the second metal at a height position equal to that of the second metal layer, in the first layer. [Fig.5]
As to claim 11, YASUHIRO teaches 11. The semiconductor device according to claim 8, wherein the third metal layer is connected to the second metal layer and serves as an anchor to support the second metal layer, and the second metal layer has a cantilever beam structure or fixed beam structure having a comb shape, a meandering shape, or a membrane shape. [Fig.5]
As to claim 12, YASUHIRO teaches 12. The semiconductor device according to claim 11, wherein the third metal layer is an electrode pad that is connectable to an external device. [Fig.5]
Conclusion
Claims 1-12 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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