DETAILED ACTION
This Office Action is in response to the preliminary amendments filed on 25 March 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 5-9, and 11-20 of U.S. Patent No. 11,955,561 (hereinafter ‘561). Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claims 21 and 28, the limitations of claims 21 and 28 of the application at hand are taught by a combination of claims (1 or 8), (3 or 11), and 15 of ‘561.
In regards to claim 22, 29, 30, the limitations of claims 22, 29, and 30 of the application at hand are taught by a combination of claims (1 or 8) of ‘561.
In regards to claims 23, 24, 31, and 37, the limitations of claims 23, 24, 31, and 37 of the application at hand are taught by a combination of claims 2, 9, or 17 of ‘561.
In regards to claim 25, 32, and 39, the limitations of claims 25, 32, and 39 of the application at hand are taught by a combination of claims 5, 12, or 19 of ‘561.
In regards to claim 26 and 33, the limitations of claims 26 and 33 of the application at hand are taught by a combination of claims 6 or 13 of ‘561.
In regards to claim 27 and 34, the limitations of claims 27 and 34 of the application at hand are taught by a combination of claims 7 or 14 of ‘561.
In regards to claim 35, the limitations of claim 34 of the application at hand are taught by a combination of claims 1, 2, 8, 9, or 17 of ‘561.
In regards to claim 36, the limitations of claim 36 of the application at hand are taught by a combination of claim 16 of ‘561.
In regards to claim 38, the limitations of claim 38 of the application at hand are taught by a combination of claim 18 of ‘561.
In regards to claim 40, the limitations of claim 40 of the application at hand are taught by a combination of claim 20 of ‘561.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 22, 28, and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Machida et al. (US 2007/0212825 A1; hereinafter Machida).
In regards to claim 21, Machida teaches, e.g. in figs. 4 and 8, a transistor structure, comprising:
a gate electrode (9) [0030];
an active layer (5a) [0031] comprising a top surface (e.g. surface towards (7)) and a bottom surface (e.g. surface towards (3));
an insulating layer (7) [0075] in contact with the gate electrode and the active layer and separating the gate electrode from the active layer (e.g. figs. 4);
a source electrode (one instance of (23)) [0082];
a drain electrode (another instance of (23)) [0082]; and
a carrier modification device in contact with the active layer, wherein the carrier modification device is configured to reduce short channel effects in the active layer ([0088-0093]: carrier variation suppression element to affect device characteristics in the channel length direction).
In regards to claim 22, Machida teaches the limitations discussed above in addressing claim 21. Machida further teaches, e.g. in figs. 4 and 8, the limitations wherein the active layer comprises one or more of amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, and alloys thereof [0031].
In regards to claim 28, Machida teaches, e.g. in figs. 4 and 8, a semiconductor structure, comprising:
a thin-film transistor structure (TFT) [0082] comprising:
a gate electrode (9) [0030];
an active layer (5a) [0031] comprising a top surface (e.g. surface towards (7)) and a bottom surface (e.g. surface towards (3));
an insulating layer (7) [0075] in contact with the gate electrode and the active layer and separating the gate electrode from the active layer (e.g. figs. 4);
a source electrode (one instance of (23)) [0082];
a drain electrode (another instance of (23)) [0082]; and
a carrier modification device in contact with the active layer ([0088-0093]: carrier variation suppression element to affect device characteristics in the channel length direction),
wherein the carrier modification device is configured to reduce short channel effects in the active layer, wherein the gate electrode, the source electrode, and the drain electrode are each disposed on the top surface of the active layer ([0088-0093]: carrier variation suppression element to affect device characteristics in the channel length direction).
In regards to claim 30, Machida teaches the limitations discussed above in addressing claim 28. Machida further teaches, e.g. in figs. 4 and 8, the limitations wherein the active layer comprises one or more of amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, and alloys thereof [0031].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida, as applied to claim(s) 21 above, in view of Maehara (US 2018/0190495 A1; hereinafter Maehara).
In regards to claim 23, Machida teaches the limitations discussed above in addressing claim 21. Machida appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises: a first injection layer in contact with the source electrode and the active layer and separating the source electrode from the active layer; a second injection layer in contact with the drain electrode and the active layer and separating the drain electrode from the active layer; and the first injection layer and the second injection layer each comprise one or more of InOx, InGaZnO, InZnO, CaOx, ZnO, CaOx/ZnO, ZnO/GaOx, TiN, TaN, Au, Pt, Ru, and alloys thereof. Maehara teaches, e.g. in fig. 3, the limitations wherein the carrier modification device comprises:
a first injection layer ([0108]: portion of (42) connected to source electrode (20)) in contact with the source electrode (20) and the active layer and separating (e.g. portions of (42) are vertically between (20) and (18)) the source electrode from the active layer (e.g. (18));
a second injection layer ([0108]: portion of (42) connected to drain electrode (24)) in contact with the drain electrode (24) and the active layer and separating (e.g. portions of (42) are vertically between (24) and (18)) the drain electrode from the active layer; and
the first injection layer and the second injection layer each comprise one or more of InOx, InGaZnO, InZnO, CaOx, ZnO, CaOx/ZnO, ZnO/GaOx, TiN, TaN, Au, Pt, Ru, and alloys thereof ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Maehara to have a higher and more stable carrier mobility using the charge injection layer (Maehara [0012]).
Claim(s) 35 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida in view of Maehara.
In regards to claim 35, Machida teaches, e.g. in figs. 4 and 8, a method of fabricating a transistor structure, comprising:
forming a gate electrode (9) [0030];
forming an active layer (5a) [0031] comprising one or more of amorphous silicon, InGaZnO, InGaO, InWO, InZnO, InSnO, ZnO, GaO, InO, and alloys thereof [0031];
forming an insulating layer (7) [0075] in contact with the gate electrode and the active layer and separating the gate electrode from the active layer (e.g. figs. 4);
forming a source electrode (one instance of (23)) [0082];
forming a drain electrode (another instance of (23)) [0082]; and
forming a carrier modification device in contact with the active layer ([0088-0093]: carrier variation suppression element to affect device characteristics in the channel length direction).
Machida appears to be silent as to, but does not preclude, the limitations of forming a carrier modification device in contact with the active layer that comprises one or more of InOx, CaOx/ZnO, ZnO/GaOx. Maehara teaches, e.g. in figs. 3, the limitations of forming a carrier modification device in contact with the active layer that comprises one or more of InOx, CaOx/ZnO, ZnO/GaOx ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Maehara to have a higher and more stable carrier mobility using the charge injection layer (Maehara [0012]).
In regards to claim 36, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 35. Maehara further teaches, e.g. in figs. 3, the limitations wherein the carrier modification device comprises:
a first injection layer ([0108]: portion of (42) connected to source electrode (20)) and a second injection layer ([0108]: portion of (42) connected to drain electrode (24)), and forming the carrier modification device comprises:
forming the first injection layer and the second injection layer each in contact with the active layer (figs. 3: (42) is in contact with (18)),
wherein the first injection layer and the second injection layer each comprise a material having a first value of electronegativity ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO) and the source electrode and the drain electrode each have a second value of electronegativity ([0065],[0054]; [0100], [0103]), and
wherein the first value of electronegativity is greater than the second value of electronegativity ([0065],[0054]; [0100], [0103]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Maehara to have a higher and more stable carrier mobility using the charge injection layer (Maehara [0012]).
Claim(s) 24 and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Machida and Maehara as applied to claim(s) 23 and 35 above, and further in view of Song et al. (US 2019/0288118 A1; hereinafter Song).
In regards to claim 24, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 23. The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm. Song teaches the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Song to improve the switching characteristics (e.g. carrier mobility) of the thin-film transistor (Song [0059]).
In regards to claim 37, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 35. Maehara further teaches, e.g. in figs. 3, the limitations wherein the carrier modification device comprises a first injection layer ([0108]: portion of (42) connected to source electrode (20)) and a second injection layer ([0108]: portion of (42) connected to drain electrode (24)), and forming the carrier modification device comprises: forming the first injection layer and the second injection layer each in contact with the active layer (figs. 3: (42) is in contact with (18)), wherein the first injection layer and the second injection layer each comprise one or more of InGaZnO, InZnO, CaOx, ZnO, TiN, TaN, Au, Pt, Ru, and alloys thereof ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO).
The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm. Song teaches the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Song to improve the switching characteristics (e.g. carrier mobility) of the thin-film transistor (Song [0059]).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida as applied to claim 28 above, in view of Maehara, and further in view of Song.
In regards to claim 31, Machida teaches the limitations discussed above in addressing claim 28. Machida appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises: a first injection layer in contact with the source electrode and the active layer and separating the source electrode from the active layer; a second injection layer in contact with the drain electrode and the active layer and separating the drain electrode from the active layer; and wherein he first injection layer and the second injection layer each comprise one or more of InOx, InGaZnO, InZnO, CaOx, ZnO, CaOx/ZnO, ZnO/GaOx, TiN, TaN, Au, Pt, Ru, and alloys thereof.
Maehara teaches, e.g. in figs. 3, the limitations wherein the carrier modification device comprises:
a first injection layer ([0108]: portion of (42) connected to source electrode (20)) in contact with the source electrode (20) and the active layer and separating (e.g. portions of (42) are vertically between (20) and (18)) the source electrode from the active layer (e.g. (18));
a second injection layer ([0108]: portion of (42) connected to drain electrode (24)) in contact with the drain electrode (24) and the active layer and separating (e.g. portions of (42) are vertically between (24) and (18)) the drain electrode from the active layer; and
wherein he first injection layer and the second injection layer each comprise one or more of InOx, InGaZnO, InZnO, CaOx, ZnO, CaOx/ZnO, ZnO/GaOx, TiN, TaN, Au, Pt, Ru, and alloys thereof ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Maehara to have a higher and more stable carrier mobility using the charge injection layer (Maehara [0012]).
The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm. Song teaches the limitations wherein the first injection layer and the second injection layer have a thickness in a range from approximately 0.1 nm to 20 nm [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Song to improve the switching characteristics (e.g. carrier mobility) of the thin-film transistor (Song [0059]).
Claim(s) 25-27, 32-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida as applied to claim(s) 21 and 28 above, and further in view of Van Dal et al. (US 2021/0376151 A1; hereinafter Van Dal).
In regards to claim 25, Machida teaches the limitations discussed above in addressing claim 21. Machida appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises: a capping layer in contact with the active layer, wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof, and wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm. Van Dal teaches the limitations wherein the carrier modification device comprises:
a capping layer (402) [0038] in contact with the active layer (404A) [0041], wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof [0038], and
wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm [0018].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 26, the combination of Machida and Van Dal teaches the limitations discussed above in addressing claim 25. Van Dal further teaches the limitations wherein the capping layer is disposed on the top surface of the active layer and is positioned symmetrically relative to the source electrode and the drain electrode ([0054]: top gate configuration). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 27, the combination of Machida and Van Dal teaches the limitations discussed above in addressing claim 25. Van Dal further teaches the limitations wherein the capping layer is disposed on the bottom surface of the active layer and is positioned symmetrically relative to the source electrode and the drain electrode ([0048]: bottom gate configuration). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 32, Machida teaches the limitations discussed above in addressing claim 28. Machida appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises: a capping layer in contact with the active layer, wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof, and wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm. Van Dal teaches the limitations wherein the carrier modification device comprises:
a capping layer (402) [0038] in contact with the active layer (404A) [0041], wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof [0038], and
wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm [0018].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 33, the combination of Machida and Van Dal teaches the limitations discussed above in addressing claim 32. Van Dal further teaches the limitations wherein the capping layer is disposed on the top surface of the active layer and is positioned symmetrically relative to the source electrode and the drain electrode ([0054]: top gate configuration). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 34, the combination of Machida and Van Dal teaches the limitations discussed above in addressing claim 32. Van Dal further teaches the limitations wherein the capping layer is disposed on the bottom surface of the active layer and is positioned symmetrically relative to the source electrode and the drain electrode ([0048]: bottom gate configuration). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
Claim(s) 38-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Machida and Maehara as applied to claim(s) 35 above, and further in view of Van Dal.
In regards to claim 38, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 35. Maehara further teaches, e.g. in figs. 3, the limitations wherein the capping layer has a first value of electronegativity and the active layer has a second value of electronegativity ([0100], [0103]: e.g. (42) equivalents of (28/30) are formed of materials such as ZnO) and the source electrode and the drain electrode each have a second value of electronegativity ([0065],[0054]; [0100], [0103]), and wherein the first value of electronegativity is greater than the second value of electronegativity ([0065],[0054]; [0100], [0103]).
The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises: forming the capping layer in contact with the active layer. Van Dal teaches the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises: forming the capping layer (402) [0038] in contact with the active layer (404A) [0041]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 39, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 35. The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises: forming the capping layer in contact with the active layer, wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof, and wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm. Van Dal teaches the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises:
forming the capping layer (402) [0038] in contact with the active layer (404A) [0041],
wherein the capping layer comprises one or more of InOx, GaOx, ZnO, IZO, CaOx/ZnO, ZnO/GaOx, Al, Mo, W, Ti, Ca, oxides thereof, and alloys thereof [0038], and
wherein the capping layer has a thickness in a range from 0.1 nm to 500 nm [0018].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
In regards to claim 40, the combination of Machida and Maehara teaches the limitations discussed above in addressing claim 35. The combination of Machida and Maehara appears to be silent as to, but does not preclude, the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises: capping layer in contact with the active layer, wherein a width of the capping layer is smaller than a distance between the source electrode and the drain electrode. Van Dal teaches the limitations wherein the carrier modification device comprises a capping layer, and forming the carrier modification device comprises:
capping layer (402) [0038] in contact with the active layer (404A) [0041],
wherein a width of the capping layer is smaller than a distance between the source electrode and the drain electrode.
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Machida and Maehara with the aforementioned limitations taught by Van Dal to have a scaling down process that generally provides benefits by increasing production and efficiently lowering associated costs (Van Dal [0002]).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida as applied to claim(s) 28 above, and further in view of Yen et al. (US 2022/0140197 A1; hereinafter Yen).
In regards to claim 29, Machida teaches the limitations discussed above in addressing claim 28. Machida further teaches, e.g. in figs. 4 and 8, the limitations comprising: a substrate (2) [0082].
Machida appears to be silent as to, but does not preclude, the limitations of a substrate comprising a plurality of CMOS transistors; and an interconnect structure having a plurality of metal interconnect level structures, wherein the thin-film transistor structure is formed in one of the plurality of metal interconnect level structures. Yen teaches the limitations of a substrate comprising a plurality of CMOS transistors (T) ([0017], [0026]); and an interconnect structure having a plurality of metal interconnect level structures (104) [0026], wherein the thin-film transistor structure is formed in one of the plurality of metal interconnect level structures (TFT) [0082] (TFT) [0026].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Machida with the aforementioned limitations taught by Yen to reduce the variation of optical transparency and/or other material properties of the transparent conductive patterns during manufacturing process, and optical performance of the electroluminescence devices can be improved (Yen [0039]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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