DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2020/0303334 to Liu et al (hereinafter Liu).
Regarding Claim 1, Liu discloses a semiconductor device comprising:
a first pillar (Fig. 1, 1063) and a second pillar (1083) formed over a substrate;
a first solder layer (1067) configured to cover a first surface of the first pillar; and
a second solder layer (1087) configured to cover a second surface of the second pillar;
wherein the first surface of the first pillar has a lower height than a height of the second surface of the second pillar (Fig. 1) and the second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface (Fig. 1), wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate (Fig. 1).
Regarding Claim 2, Liu discloses the semiconductor device of Claim 1, wherein:
a first height of the first surface of the first pillar is a first distance from a surface of the substrate, and a second height of the second surface of the second pillar is a second distance from the surface of the substrate (fig. 1), and
a first thickness of the first solder layer is a distance from the first surface to a first end of the first solder layer, and a second thickness of the second solder layer is a distance from the second surface to a second end of the second solder layer (Fig. 1),
wherein the first end of the first solder layer is an end of the first solder layer farthest from the first pillar, and the second end of the second solder layer is an end of the second solder layer farthest from the second pillar (Fig. 1).
Regarding Claim 3, Liu discloses the semiconductor device of Claim 1, wherein the substrate comprises a conductive pad (110) connected to the first pillar.
Regarding Claim 4, Liu discloses the semiconductor device of Claim 3, further comprising, on the substrate, a dielectric layer (104) that exposes the conductive pad, wherein the second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer (Fig. 1).
Regarding Claim 5, Liu discloses the semiconductor device of Claim 4, further comprising:
a first underlying layer (1061) formed between the first pillar and the conductive pad; and
a second underlying layer (1081) formed between the second pillar and the dielectric layer.
Regarding Claim 6, Liu discloses the semiconductor device of Claim 1, wherein the second pillar has a thickness identical to a thickness of the first pillar or has a thickness greater than the thickness of the first pillar [0047].
Regarding Claim 7, Liu discloses the semiconductor device of Claim 1, wherein the second pillar has a width identical to a width of the first pillar or has a width greater than the width of the first pillar [0028].
Regarding Claim 8, Liu discloses a semiconductor device comprising:
a first substrate (102, Fig. 1);
a second substrate (101, Fig. 5) that is disposed over the first substrate and that comprises a first conductive trace (518) and a second conductive trace (519);
a first pillar (1063) and a second pillar (1083) disposed between the first substrate and the second substrate;
a first solder layer (1067) configured to cover a first surface of the first pillar; and
a second solder layer (1087) configured to cover a second surface of the second pillar;
wherein the first surface of the first pillar has a lower height than a height of the second surface of the second pillar (Fig. 1), wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate (Fig. 1), and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate (Fig. 1);
wherein the first solder layer is connected to the first conductive trace (Fig. 5);
wherein the second solder layer is connected to the second conductive trace (Fig. 5); and
wherein a distance between the first surface and the first conductive trace is greater than a distance between the second surface and the second conductive trace (Fig. 5).
Regarding Claim 9, Liu discloses the semiconductor device of Claim 8, wherein
the first substrate comprises a conductive pad (110) connected to the first pillar;
wherein the semiconductor device further comprises, on the substrate, a dielectric layer (104) that exposes the conductive pad; and
wherein the second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer (Fig. 1).
Regarding Claim 10, Liu discloses the semiconductor device of Claim 9, wherein the first substrate further comprises:
conductive vias configured to support the conductive pad [0022];
conductive patterns connected to the conductive pad by the conductive vias [0022]; and
an insulating layer configured to insulate the conductive vias and the conductive patterns [0022];
wherein the dielectric layer comprises:
a first dielectric layer (112) that exposes a section of the conductive pad and that comprises an inorganic insulating layer [0023]; and
a second dielectric layer (104) that is disposed on the first dielectric layer and that comprises a carbon polymer insulating layer [0023].
Regarding Claim 11, Liu discloses a method of manufacturing a semiconductor device, comprising:
forming a first pillar and a second pillar over a substrate (Fig. 7(d);
forming a first resist pattern (714) comprising a first opening that exposes a first surface of the first pillar and comprising a second opening that exposes a second surface of the second pillar and that has a smaller width than the width of the first opening, wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate [0028];
forming a first solder pattern (1068, Fig. 7(e)) within the first opening and a second solder pattern (1088) within the second opening;
removing the first resist pattern (Fig. 7(f); and
forming a first solder layer by reflowing the first solder pattern and forming a second solder layer by reflowing the second solder pattern [0050].
Regarding Claim 12, Liu discloses the method of Claim 11, wherein the first pillar and the second pillar are formed such that the first surface of the first pillar has a lower height than the second surface of the second pillar (Fig. 7(d)).
Regarding Claim 13, Liu discloses the method of Claim 12, wherein the second solder layer is formed having a smaller thickness than the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface [0026].
Regarding Claim 14, Liu discloses the method of Claim 11, wherein the second solder pattern is formed having a smaller volume than the first solder pattern due to a difference between a width of the first opening and a width of the second opening (Fig. 7(e)).
Regarding Claim 15, Liu discloses the method of Claim 11, wherein:
the substrate comprise a conductive pad (110), and the first pillar is connected to the conductive pad.
Regarding Claim 16, Liu discloses the method of Claim 15, further comprising forming, over the substrate, a dielectric layer (104) that exposes the conductive pad, wherein the second pillar is connected to the dielectric layer and formed such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer (Fig. 1).
Regarding Claim 17, Liu discloses the method of Claim 16, wherein the forming the first pillar and the second pillar comprises:
forming a seed layer for plating, which covers the conductive pad and extends to cover the dielectric layer [0046];
forming a second resist pattern comprising a third opening that overlaps the conductive pad and a fourth opening that overlaps the dielectric layer [0047]; and
plating the first pillar within the first opening, and plating the second pillar within the fourth openings [0048].
Regarding Claim 18, Liu discloses the method of Claim 11, wherein the first solder pattern is formed by plating a solder material within the first opening, and the second solder pattern is formed by plating a solder material within the second opening [0048].
Regarding Claim 19, Liu discloses the method of Claim 11, wherein the second pillar is formed having a thickness identical to a thickness of the first pillar or having a greater thickness than the thickness of the first pillar [0047].
Regarding Claim 20, Liu discloses the method of Claim 11, wherein the second pillar is formed having a width identical to a width of the first pillar or having a greater width than the width of the first pillar [0028].
Regarding Claim 21, Liu discloses a semiconductor device comprising:
a first pillar (1063) and a second pillar (1083) formed over a substrate (Fig. 1);
a first solder layer (1067) configured to cover a first surface of the first pillar; and
a second solder layer (1087) configured to cover a second surface of the second pillar;
wherein the second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface (Fig. 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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