The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 1-20 rejected under 35 U.S.C. 103(a) as being unpatentable over KIM et al. (U.S. Patent Application Publication 2020/0251494, hereinafter referred to as KIM) in view of Lai (U.S. Patent Application Publication 2014/0264353, hereinafter referred to as Lai).
As to claim 1, KIM teaches 1. A non-volatile memory device comprising: a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes sequentially stacked on the memory cell region and stacked stepwise on the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes; a channel hole vertically passing through the mold structure on the memory cell region; and a channel structure disposed in the channel hole, wherein the channel structure includes a gate insulating layer, a channel layer, and a buried insulating layer sequentially disposed in the channel hole. [see 4~11 for example]
KIM may not explicitly teach the channel layer includes a grain having a size of about 20 nm to about 17 μm.
Lai teaches this limitation [¶0048~0049 for example]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of KIM and Lai to “larger grain size polysilicon crystals" in KIM according to Lai, for the further advantage of “increased grain sizes of silicon crystals in polycrystalline silicon used to form channel regions of memory cells can improve the channel performance”. [Lai ¶0049]
As to claim 2, KIM and Lai teaches 2. The non-volatile memory device of claim 1, wherein the channel layer includes a silicon channel layer, and a size of the grain of the silicon channel layer is about 20 nm to about 17 μm. [Lai ¶0048~0049]
As to claim 3, KIM and Lai teaches 3. The non-volatile memory device of claim 1, wherein the grain of the channel layer overlaps the plurality of gate electrodes in a horizontal direction. [KIM ¶0087-0088]
As to claim 4, KIM and Lai teaches 4. The non-volatile memory device of claim 1, wherein the channel layer is apart from the substrate. [KIM Fig. 11]
As to claim 5, KIM and Lai teaches 5. The non-volatile memory device of claim 4, further comprising a source layer disposed between the substrate and the mold structure, wherein the channel layer is in contact with the source layer. [KIM Fig. 4]
As to claim 6, KIM and Lai teaches 6. The non-volatile memory device of claim 5, wherein the source layer passes through the gate insulating layer and contacts an outer wall of the channel layer. [KIM Fig. 4]
As to claim 7, KIM and Lai teaches 7. The non-volatile memory device of claim 5, wherein the source layer is in contact with a lower surface of the channel layer. [KIM Fig. 4, 11]
As to claim 8, KIM and Lai teaches 8. The non-volatile memory device of claim 5, wherein the source layer includes doped polycrystalline silicon. [KIM Fig. 4, 11]
As to claim 9, KIM and Lai teaches 9. The non-volatile memory device of claim 4, wherein the substrate includes single-crystal silicon. [KIM Fig. 4, 11]
As to claim 10, KIM and Lai teaches 10. A non-volatile memory device comprising: a peripheral circuit structure and a cell array structure sequentially stacked on a substrate, wherein the cell array structure includes: a mold structure including a plurality of gate electrodes sequentially stacked on a memory cell region of the substrate and stacked stepwise on a connection region of the substrate, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes; and a channel layer vertically passing through the mold structure on the memory cell region and intersecting with the plurality of gate electrodes, wherein the channel layer includes a grain having a size of about 20 nm to about 17 μm. [see rejection claim 1 above]
As to claim 11, KIM and Lai teaches 11. The non-volatile memory device of claim 10, further comprising: a gate insulating layer extending in a vertical direction between the channel layer and the mold structure; and a buried insulating layer apart from the gate insulating layer with the channel layer therebetween. [KIM Fig. 4, 11]
As to claim 12, KIM and Lai teaches 12. The non-volatile memory device of claim 11, wherein the gate insulating layer includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially disposed on an outer wall of the channel layer. [KIM Fig. 4, 11]
As to claim 13, KIM and Lai teaches 13. The non-volatile memory device of claim 10, wherein the grain of the channel layer overlaps the plurality of gate electrodes in a horizontal direction. [KIM Fig. 4, 11]
As to claim 14, KIM and Lai teaches 14. The non-volatile memory device of claim 10, further comprising a source layer disposed between the substrate and the mold structure, wherein the channel layer is apart from the substrate with the source layer therebetween. [KIM Fig. 4, 11]
As to claim 15, KIM and Lai teaches 15. The non-volatile memory device of claim 14, wherein the substrate includes single-crystal silicon, and the source layer includes doped polycrystalline silicon. [KIM Fig. 4, 11]
As to claim 16, KIM and Lai teaches 16. The non-volatile memory device of claim 14, further comprising a gate insulating layer extending in a vertical direction between the channel layer and the mold structure, wherein the source layer passes through the gate insulating layer and contacts the channel layer. [KIM Fig. 4, 11]
As to claim 17, KIM and Lai teaches 17. The non-volatile memory device of claim 14, wherein the source layer is in contact with a lower surface of the channel layer. [KIM Fig. 4, 11]
As to claim 18, KIM and Lai teaches 18. The non-volatile memory device of claim 14, wherein the peripheral circuit structure includes a peripheral circuit transistor; a peripheral circuit wiring structure electrically connected to the peripheral circuit transistor; and an interlayer insulating layer covering the peripheral circuit wiring structure, and the interlayer insulating layer is in contact with the source layer. [KIM Fig. 4, 11]
As to claim 19, KIM and Lai teaches 19. An electronic system comprising: a main board; a non-volatile memory device on the main board; and a controller electrically connected to the non-volatile memory device on the main board, wherein the non-volatile memory device includes: a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes sequentially stacked on the memory cell region and stacked stepwise on the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes; a source layer disposed between the substrate and the mold structure; a channel hole vertically passing through the mold structure on the memory cell region; and a channel structure disposed in the channel hole, wherein the channel structure includes a gate insulating layer, a silicon channel layer, and a buried insulating layer sequentially disposed in the channel hole, the silicon channel layer is apart from the substrate with the source layer therebetween, and the silicon channel layer includes a silicon grain having a size of about 20 nm to about 17 μm.[see rejection claim 1 above]
As to claim 20, KIM and Lai teaches 20. The electronic system of claim 19, wherein the silicon grain of the silicon channel layer overlaps the plurality of gate electrodes in a horizontal direction. [KIM Fig. 4, 11]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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