DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 06/05/2026 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/05/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2021/0193581 to Seo et al (hereinafter Seo) in view of US PG Pub 2022/0328467 to Chen et al (hereinafter Chen).
Regarding Claim 1, Seo discloses a three-dimensional (3D) integrated circuit structure comprising:
a redistribution structure (142, Fig. 1);
a first semiconductor die (110) on the redistribution structure;
a substrate (130) on the redistribution structure and adjacent to the first semiconductor die;
a molding material (163) on the redistribution structure and between the first semiconductor die and the substrate;
an interconnection structure on the substrate and the first semiconductor die, the interconnection structure comprising a plurality of first bonding pads (135) and a plurality of second bonding pads (127), and each second bonding pad of the plurality of second bonding pads being directly bonded to each first bonding pad of the plurality of first bonding pads (see below); and
a second semiconductor die (121) on the interconnection structure.
Seo does not disclose the first and second bonding pads to be directly bonded to each other
Chen discloses bonding pads (66/114, Fig. 4) that are directly bonded to each other [0033].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have directly bonded the first and second bonding pads of Seo. Hybrid bonding processes were known in the art, before the invention, to directly bond metal layers together. The process achieves known benefits such as increasing chip density and boosting signal speed.
Regarding Claim 2, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 1, wherein a footprint of the first semiconductor die and a footprint of the substrate are included within a footprint of the second semiconductor die (Fig. 1).
Regarding Claim 3, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 1, wherein the substrate is adjacent to a first side surface of the first semiconductor die (Fig. 1).
Regarding Claim 4, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 3, further comprising at least one additional substrate on the redistribution structure and adjacent to the first semiconductor die, the at least one additional substrate being molded by the molding material (Fig. 1).
Regarding Claim 5, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 4, wherein one substrate of the at least one additional substrate is adjacent to a second side surface of the first semiconductor die opposite to the first side surface (Fig. 1).
Regarding Claim 6, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 1, wherein the substrate is adjacent to at least one side surface of the first semiconductor die (Fig. 1).
Regarding Claim 7, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 1, wherein the substrate comprises an embedded trace substrate (ETS) (Fig. 1).
Regarding Claim 8, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 1, wherein the 3D integrated circuit structure is a system on chip (SOC) (Fig. 1, [0037].
Regarding Claim 9, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of claim 1, wherein the first semiconductor die comprises at least one of a central processing unit (CPU) and a graphics processing unit (GPU), and wherein the second semiconductor die comprises at least one of a sensor or a communication chip [0037].
Regarding Claim 10, Seo discloses a three-dimensional (3D) integrated circuit structure comprising:
a redistribution structure (Fig. 1, 142) comprising a plurality of redistribution vias;
a first semiconductor die (110) on the redistribution structure;
a substrate (130) on the redistribution structure and adjacent to the first semiconductor die;
a molding material (163) on the redistribution structure and molding the first semiconductor die and the substrate;
an interconnection structure on the substrate and the first semiconductor die, the interconnection structure comprising:
a plurality of first bonding pads (135);
a plurality of second bonding pads (127); and
a second semiconductor die (121) on the interconnection structure.
Seo does not disclose a first silicon insulating layer adjacent to side surfaces of the plurality of first bonding pads; and
a second silicon insulating layer adjacent to side surfaces of the plurality of second bonding pads, each second bonding pad of the plurality of second bonding pads being directly bonded to each first bonding pad of the plurality of first bonding pads.
Chen discloses a first silicon insulating layer (112) adjacent to side surfaces of the plurality of first bonding pads (114); and
a second silicon insulating layer (68) adjacent to side surfaces of the plurality of second bonding pads (66), each second bonding pad of the plurality of second bonding pads being directly bonded to each first bonding pad of the plurality of first bonding pads.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have directly bonded the first and second bonding pads of Seo. Hybrid bonding processes were known in the art, before the invention, to directly bond metal layers together. The process achieves known benefits such as increasing chip density and boosting signal speed.
Regarding Claim 11, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 10, wherein the first semiconductor die comprises:
a plurality of first connection pads (not pictured);
a plurality of second connection pads (117); and
a plurality of through silicon vias(115), wherein a first end of each through silicon via among the through silicon vias contacts each first connection pad among the plurality of first connection pads, and wherein a second end of each through silicon via contacts each second connection pad among the second connection pads (Fig. 1).
Regarding Claim 12, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 11, wherein each of the plurality of first connection pads is directly bonded to each of a portion of redistribution vias among the redistribution vias (Fig. 1).
Regarding Claim 13, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 11, wherein each of the second connection pads is directly bonded to each of a portion of first bonding pads among the plurality of first bonding pads (Fig. 1).
Regarding Claim 14, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 10, wherein the substrate comprises a plurality of wiring layers, and wherein each wiring layer at a lowermost level among the wiring layers is directly bonded to each of a portion of redistribution vias among the redistribution vias (Fig. 1) since it would have been obvious to form a multilevel metallization interconnect in place of a through via.
Regarding Claim 15, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 10, wherein a width of an uppermost portion in each redistribution via among the redistribution vias is smaller than a width of a lowermost portion in each redistribution via among the redistribution vias since it would have been obvious to form V-shaped vias to prevent air gaps.
Regarding Claim 16, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 10, wherein the second silicon insulating layer is directly bonded to the first silicon insulating layer (Fig. 4, Chen).
Regarding Claim 17, the combination of Seo and Chen makes obvious the 3D integrated circuit structure of Claim 10, wherein an upper surface of the first semiconductor die is coplanar with an upper surface of the substrate (Fig. 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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