DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 9 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2003/0156743 to Okada et al (hereinafter Okada).
Regarding Claim 1, Okada discloses a semiconductor device comprising:
a first substrate (Fig. 1, 8);
a second substrate (12) provided to face the first substrate;
a chip (2) provided on the first substrate and between the first substrate and the second substrate; and
a spacer (14) provided on the chip and coupling the chip and the second substrate, wherein the spacer includes a first portion in contact with the chip and a second portion in contact with the second substrate, and the second portion is larger in area than the first portion (Fig. 1).
Regarding Claim 2, Okada discloses the device according to Claim 1, wherein the first portion of the spacer is fittable within a surface of the chip, the surface being in contact with the spacer (Fig. 1).
Regarding Claim 5, Okada discloses the device according to Claim 1, wherein the spacer includes a portion in which a side wall is inclined from the first portion to the second portion (Fig. 1).
Regarding Claim 6, Okada discloses the device according to Claim 1, wherein the spacer includes a cross-sectional area on a plane in parallel to the first substrate, and the cross-sectional area continuously increases from the first portion to the second portion (Fig. 1).
Regarding Claim 9, Okada discloses the device according to Claim 1, wherein the spacer includes a first component including the first portion and a second component including the second portion, and the spacer has a shape in which the second component protrudes from all of four sides above the first component (Fig. 6).
Regarding Claim 12, Okada discloses t1he device according to claim 1, wherein the spacer includes a first component including the first portion and a second component including the second portion, and the first component and the second component are directly coupled not via a joint layer (Fig. 1).
Claims 1, 3, 7 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2025/0233032 to Yoon et al (hereinafter Yoon).
Regarding Claim 1, Yoon discloses a semiconductor device comprising:
a first substrate (Fig. 1, 10/11/12);
a second substrate (not pictured [0036]) provided to face the first substrate;
a chip (20) provided on the first substrate and between the first substrate and the second substrate; and
a spacer (56/57/30) provided on the chip and coupling the chip and the second substrate, wherein the spacer includes a first portion in contact with the chip and a second portion in contact with the second substrate, and the second portion is larger in area than the first portion (Fig. 1).
Regarding Claim 3, Yoon discloses the device according to Claim 1, wherein the spacer is larger in thermal expansion coefficient than the chip and is smaller in thermal expansion coefficient than copper included in the first substrate and the second substrate [0035].
Regarding Claim 7, Yoon discloses the device according to Claim 1, wherein the spacer includes a first component including the first portion (57) and a second component (56) including the second portion, and the first component and the second component are joined via a joint layer.
Regarding Claim 8, Yoon discloses the device according to Claim 7, wherein the joint layer includes solder [0032].
Claims 1, 4, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2019/0341332 to Lin et al (hereinafter Lin).
Regarding Claim 1, Lin discloses a semiconductor device comprising:
a first substrate (180, Fig. 3);
a second substrate (140) provided to face the first substrate;
a chip (310a) provided on the first substrate and between the first substrate and the second substrate; and
a spacer (313a/320a/314a) provided on the chip and coupling the chip and the second substrate, wherein the spacer includes a first portion in contact with the chip and a second portion in contact with the second substrate, and the second portion is larger in area than the first portion (Fig. 3).
Regarding Claim 4, Lin discloses the device according to Claim 1, wherein the chip includes a transistor, and the spacer electrically couples one end of a current path of the transistor and the second substrate [0031].
Regarding Claim 10, Lin discloses the device according to Claim 1, wherein the spacer includes a first component including the first portion (313a), a second component (314a) including the second portion, and a third component (320a) provided between the first component and the second component, the first component includes an upper surface and a lower surface which are fittable within an upper surface of the chip, the third component includes an upper surface and a lower surface within which an upper surface of the first component is fittable, and the second component includes an upper surface and a lower surface within which an upper surface of the third component is fittable (Fig. 3).
Regarding Claim 11, Lin discloses the device according to claim 10, wherein the first component and the third component are joined via a joint layer, and the third component and the second component are joined via a joint layer [0031].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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