DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed January 12, 2026.
Claims 1-20 are pending. Claims 1-2, 5, 12, 14-15 and 20 are amended. Claims 1, 14 and 20 are independent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (U.S. 2016/0099070; hereinafter “Jiang”) in view of Mokhlesi et al. (U.S. 2007/0171744; hereinafter “Mokhlesi”).
Regarding independent claim 1, Jiang teaches a non-volatile storage apparatus (Fig. 3), comprising:
a first set of non-volatile memory cells (“non-volatile storage elements,” see Abstract); and
a control circuit (Fig. 7: 720) connected to the first set of non-volatile memory cells (“non-volatile storage elements,” see Abstract), the control circuit is configured to:
perform a programming process to program the first set of non-volatile memory cells to multiple data states (see page 5, par. 0068), each data state corresponds to a different threshold voltage distribution (Fig. 13A), and
during the programming process, perform program-verify for the first set of non-volatile memory cells including applying a first word line voltage to the first set of non-volatile memory cells for verifying for all data states of the multiple data states being verified (see page 6, par. 0072) and sensing for different current levels for different data states of the multiple data states (see page 8, par. 0095).
However, Jiang is silent with respect to verifying for all data states of the multiple data states being verified in response to the first word line voltage being applied to the first set of non-volatile memory cells.
Similar to Jiang, Mokhlesi teaches a non-volatile storage apparatus (Fig. 1), comprising a first set of non-volatile memory cells (“selected memory cells,” see Abstract), and control circuit (Fig. 1: 2-8 and 20) connected to the first set of non-volatile memory cells (“selected memory cells,” see Abstract), the control circuit is configured to perform a programming process to program the first set of non-volatile memory cells to multiple data states.
Furthermore, Mokhlesi teaches during the programming process, perform program-verify for the first set of non-volatile memory cells (see page 2, par. 0011) including applying a first word line voltage to the first set of non-volatile memory cells for verifying for all data states of the multiple data states being verified in response to the first word line voltage being applied to the first set of non-volatile memory cells (Fig. 11: Vwl, see also pages 7-8, par. 0065-0066).
Since Mokhlesi and Jiang are from the same field of endeavor, the teachings described by Mokhlesi would have been recognized in the pertinent art of Jiang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Mokhlesi with the teachings of Jiang for the purpose of reduce the number of verify reads needed between each programming pulse and improve memory performance, see Mokhlesi’s page 11, par. 0087.
Regarding claim 2, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches the control circuit is configured to perform program-verify for the first set of non-volatile memory cells by applying the first word line voltage to the first set of non-volatile memory cells during program-verify regardless of which data state the respective non-volatile memory cells is being programmed to and sensing current in response to the first word line voltage (see page 6, par. 0072).
Regarding claim 3, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches wherein the control circuit is configured to perform the programming process to program the first set of non-volatile memory cells to multiple data states by applying a set of doses of programming to the first set of non-volatile memory cells (see page 5, par. 0070); and
the control circuit is configured to perform program-verify for the first set of non-volatile memory cells including applying the first word line voltage to the first set of non-volatile memory cells for all data states of the multiple data states and sensing for different current levels for different data states of the multiple data states between doses of programming (see page 6, par. 0072).
Regarding claim 4, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches wherein the control circuit is configured to perform the programming process to program the first set of non-volatile memory cells to multiple data states by applying a set of program voltage pulses to the first set of non-volatile memory cells (see page 5, par. 0070); and
the control circuit is configured to perform program-verify for the first set of non-volatile memory cells including applying the first word line voltage to the first set of non-volatile memory cells for all data states of the multiple data states and sensing for different current levels for different data states of the multiple data states between program voltage pulses (see page 6, par. 0072).
Regarding claim 5, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches a first word line, the first set of non-volatile memory cells are all connected to the first word line (“selected word line,” see page 6, par. 0072); and
the control circuit is configured to apply the first word lie voltage to the first word line (“selected word line,” see page 6, par. 0072).
Regarding claim 6, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches the control circuit is configured to perform a read operation for the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding claim 7, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches wherein the control circuit is configured to perform an artificial intelligence inference operation for the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding claim 8, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches wherein the control circuit is configured to perform a matrix multiplication operation with the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding claim 9, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches wherein the control circuit is configured to sense for different current levels for different data states of the multiple data states by sensing at different sense times for different data states of the multiple data states (time for sensing for verify at Vv’ and time for sensing for verify at Vv, see page 8, par. 0095).
Regarding claim 13, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches the first set of non-volatile memory cells are positioned on different vertical NAND strings of a three dimensional non-volatile memory structure (see page 4, par. 0055).
Regarding independent claim 14, Jiang teaches a method, comprising:
performing a programming process to program a first set of non-volatile memory cells to multiple data states (see page 5, par. 0068), each data state corresponding to a different threshold voltage distribution (Fig. 13A); and
during the programming process, performing program-verify for the first set of non-volatile memory cells being programmed including applying a same word line voltage to the first set of non-volatile memory cells being programmed for verifying for all of the data states being verified (see page 6, par. 0072) and sensing at different sense times for different data states of the multiple data states (see page 8, par. 0095).
However, Jiang is silent with respect to sensing at different sense times for different data states of the multiple data states in response to the same word line voltage.
Similar to Jiang, Mokhlesi teaches a method, comprising performing a programming process to program a first set of non-volatile memory cells to multiple data states (see page 2, par. 0011).
Furthermore, Mokhlesi teaches sensing at different sense times for different data states of the multiple data states in response to the same word line voltage (Fig. 11: Vwl, see also pages 7-8, par. 0065-0066).
Since Mokhlesi and Jiang are from the same field of endeavor, the teachings described by Mokhlesi would have been recognized in the pertinent art of Jiang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Mokhlesi with the teachings of Jiang for the purpose of reduce the number of verify reads needed between each programming pulse and improve memory performance, see Mokhlesi’s page 11, par. 0087.
Regarding claim 15, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 14.
Furthermore, Jiang teaches the performing program-verify for the first set of non-volatile memory cells being programmed includes applying the same word line voltage to the first set of non-volatile memory cells being programmed during program-verify regardless of which data state the respective non-volatile memory cells is being programmed to and sensing current at least partially in response to the first word line voltage (see page 6, par. 0072).
Regarding claim 16, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 14.
Furthermore, Jiang teaches performing a programming process comprises applying a set of doses of programming to the first set of non-volatile memory cells (see page 5, par. 0070); and
the performing program-verify comprises applying the same word line voltage to the first set of non-volatile memory cells being programmed for all data states and sensing for different current levels for different data states between doses of programming (see page 6, par. 0072).
Regarding claim 17, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 14.
Furthermore, Jiang teaches performing a read operation for the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding claim 18, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 17.
Furthermore, Jiang teaches wherein the read operation comprises an artificial intelligence inference operation for the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding claim 19, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 17.
Furthermore, Jiang teaches wherein the read operation comprises a matrix multiplication operation with the first set of non-volatile memory cells including sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells (see page 9, par. 0106 and page 12, par. 0157).
Regarding independent claim 20, Jiang teaches a non-volatile storage apparatus (Fig. 3), comprising:
a first word line (“selected word line,” see page 6, par. 0072);
a bit line (Fig. 2: 111);
a plurality of non-volatile memory cells connected to a first word line (“selected word line,” see page 6, par. 0072), multiple non-volatile memory cells of the plurality of non-volatile memory cells are connected to the bit line (see page 3, par. 0052); and
a control circuit (Fig. 7: 720) connected to the first word line and the first set of non-volatile memory cells (“non-volatile storage elements,” see Abstract), the control circuit is configured to:
apply a set of doses of programming to the first set of non-volatile memory cells connected to the first word line to program the first set of non-volatile memory cells to multiple data states (see page 5, par. 0070), each data state corresponding to a different threshold voltage distribution (Fig. 13A),
between doses of programming, perform program-verify for the first set of non-volatile memory cells being programmed including applying a first word line voltage to the first word line for verifying for all data states being verified (see page 6, par. 0072) and sensing at different sense times for each data state of all of the data states being verified (time for sensing for verify at Vv’ and time for sensing for verify at Vv, see page 8, par. 0095).
However, Jiang is silent with respect to perform a read operation for the first set of non-volatile memory cells including concurrently sensing current from the multiple non-volatile memory cells connected to the bit line in response to applying the first word line voltage to the first word line.
Mokhlesi teaches perform a read operation for the first set of non-volatile memory cells including concurrently sensing current from the multiple non-volatile memory cells connected to the bit line in response to applying the first word line voltage to the first word line (Fig. 11: Vwl, see also pages 7-8, par. 0065-0066).
Since Mokhlesi and Jiang are from the same field of endeavor, the teachings described by Mokhlesi would have been recognized in the pertinent art of Jiang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Mokhlesi with the teachings of Jiang for the purpose of reduce the number of verify reads needed between each programming pulse and improve memory performance, see Mokhlesi’s page 11, par. 0087.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang and Mokhlesi as applied to claim 1 above, and further in view of Nguyen et al. (U.S. 10,643,695; hereinafter “Nguyen”).
Regarding claim 10, Jiang in combination with Mokhlesi teaches the limitations with respect to claim 1.
Furthermore, Jiang teaches a second set of non-volatile memory cells connected to the control circuit, and a set of bit lines, each bit line of the set of bit lines is connected to one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells (see page 2, par. 0040).
However, the combination is silent with respect to the control circuit is further configured to perform a read operation for the first set of non-volatile memory cells and the second set of non-volatile memory cells by concurrently sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells and to the second set of non-volatile memory cells such that each bit line concurrently receives current from one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells.
Similar to Jiang and Mokhlesi, Nguyen teaches a non-volatile storage apparatus (Fig. 1) comprising a first set of non-volatile memory cells (Fig. 4), a control circuit, a second set of non-volatile memory cells (Fig. 4) and a set of bit lines (Fig. 4: 311-319).
Furthermore, Nguyen teaches the control circuit (Fig. 1A: 110 and 122) is further configured to perform a read operation for the first set of non-volatile memory cells and the second set of non-volatile memory cells by concurrently sensing current in response to applying the first word line voltage to the first set of non-volatile memory cells and to the second set of non-volatile memory cells such that each bit line concurrently receives current from one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells (see col. 3, ll. 42-61).
Since Nguyen, Mokhlesi and Jiang are from the same field of endeavor, the teachings described by Nguyen would have been recognized in the pertinent art of Jiang in combination with Mokhlesi.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Nguyen with the teachings of Jiang in combination with Mokhlesi for the purpose of improve performance of the sensing operation, see Nguyen’s col. 3, ll. 42-43.
Regarding claim 11, Jiang in combination with Mokhlesi and Nguyen teaches the limitations with respect to claim 10.
Furthermore, Nguyen teaches wherein the control circuit comprises a plurality of sense amplifiers connected to the bit lines such that during a read operation each sense amplifier of the plurality of sense amplifiers receives and reads current from one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells (“sense amplifiers for the different memory cells can bias their bit lines,” see col. 3, ll. 42-61).
Regarding claim 12, Jiang in combination with Mokhlesi and Nguyen teaches the limitations with respect to claim 10.
Furthermore, Jiang teaches a first word line, the first set of non-volatile memory cells and the second set of non-volatile memory cells are connected to the first word line (“selected word line,” see page 6, par. 0072).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825