DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12, 13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Youssef et al. (US 20150070803 A1, cited by the applicant) in view of Kasha et al. (US 20070052482 A1) and further in view of Stockinger et al. (“Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies”, 2003 Electrical Overstress/Electrostatic Discharge Symposium, Publisher: IEEE).
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Fig. 11 of Youssef reproduced by the examiner for ease of reference.
Regarding claims 1, 7, 14 and 20, Youssef teaches an integrated circuit having a voltage source pin, specifically showing pad 201 coupling an externally provided supply voltage to a supply rail 299.
Youssef also teaches an amplifier core (cascode amplifier 210 incorporating input transistor M1 and cascode transistor M2).
Youssef teaches an amplifier lacking a respective DC blocking input capacitor, as pad 202 is directly connected to the gate of M1 without a series capacitor, as depicted in Figure 11.
Youssef teaches a voltage source terminal, an input terminal, and an output terminal.
Youssef teaches an electro-static discharge (ESD) protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential. Specifically, Figure 11 shows diode D1 coupling the input pad 202 to the VDD rail 299, and diode D2 coupling the input pad 202 to the ground rail 298.
Youssef teaches an ESD clamp coupled between the reference potential and the voltage source terminal, specifically shown as Supply clamp 220 between rails 299 and 298.
Youssef, however, focuses on a single amplifier core and does not explicitly teach a plurality of low-noise amplifiers integrated on the same circuit. Youssef also depicts a centralized "Supply clamp 220" and does not explicitly teach that the ESD clamp is a distributed electro-static discharge clamp.
Kasha, which is in the same field of endeavor of integrated RF receivers, teaches an integrated circuit architecture comprising a plurality of low-noise amplifiers. Specifically, Kasha discloses a first LNA 102A for FM signals and a second LNA 102B for AM signals on the same integrated circuit 196 (Fig. 1C).
Both Youssef and Kasha are missing the "distributed electro-static discharge clamp," which is explicitly taught by Stockinger. Stockinger teaches a "distributed active MOSFET rail clamp network" where the ESD clamp is broken into smaller clamp devices distributed in parallel across the respective pad cells of the IC, coupled between the reference potential and the voltage source.
It would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) to modify the integrated circuit of Youssef to include a plurality of low-noise amplifiers, as taught by Kasha, to support multiple distinct RF inputs on a single chip.
Furthermore, it would have been obvious to a PHOSITA to modify the centralized supply clamp of the combined Youssef and Kasha architecture to be a distributed electro-static discharge clamp, as taught by Stockinger.
The motivation to incorporate a plurality of low-noise amplifiers into the integrated circuit is to support multi-band signal reception (e.g., AM and FM spectrums) on a single, space-efficient integrated receiver chip.
Again, the motivation to replace a centralized supply clamp with a distributed ESD clamp is to solve the problem of bus resistance causing unequal protection across distant pads. Stockinger explicitly notes that distributing the ESD clamp across the plurality of pad cells minimizes the impact of power rail resistance, ensures uniform ESD protection across all input pads in the IC regardless of location, and utilizes the total available layout area in a highly efficient manner. Incorporating this into the DC-coupled, multi-LNA architecture would ensure that all amplifier inputs are robustly and equally protected.
Regarding Claims 2 and 8 (Dual-Diode Input Protection), Youssef teaches an electro-static discharge protection circuit comprising a first diode having an anode coupled to the reference potential and a cathode coupled to the input terminal, and a second diode having an anode coupled to the input terminal and a cathode coupled to the voltage source terminal. Specifically, Figure 11 of Youssef shows diode D2 having its anode coupled to ground 298 (reference potential) and cathode to the input pad 202 (input terminal), and diode D1 having its anode coupled to the input pad 202 and cathode to supply rail 299 (voltage source terminal).
Youssef, however, focuses on a single amplifier and a centralized clamp, missing the plurality of LNAs and distributed clamp architecture of the independent claims.
Kasha, in a similar field of endeavor, teaches the plurality of LNAs. Stockinger teaches the distributed electro-static discharge clamp.
It would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) to apply the specific dual-diode input protection topology taught by Youssef to each LNA input port within the multi-LNA, distributed-clamp architecture of Kasha and Stockinger.
The motivation is to safely shunt both positive and negative ESD transients away from the sensitive LNA input gates directly to the power and ground rails, preventing gate-oxide rupture during an ESD event.
Regarding Claims 3, 9, and 15 (Schottky Diodes)
Youssef teaches that the first and second diodes of the ESD protection circuit may be a Schottky diode. Youssef explicitly states that "any of a junction diode, a gated diode, a silicon-controlled rectifier, and a Schottky diode, etc., may be used".
Youssef misses the plurality of LNAs and the distributed clamp architecture.
Kasha teaches the plurality of LNAs. Stockinger teaches the distributed electro-static discharge clamp.
It would have been obvious to a PHOSITA to select Schottky diodes for the dual-diode input protection circuitry of the combined Youssef/Kasha/Stockinger architecture.
The motivation to use Schottky diodes instead of standard PN junction diodes is their inherently low forward voltage drop and fast switching speeds, which provide faster reaction times to sudden, high-voltage ESD transients, thereby improving the overall protection of the integrated circuit.
Regarding Claims 4, 10, and 16 (Specific RC-Inverter Clamp Topology)
Youssef teaches a basic supply clamp 220 between the voltage source and reference but does not detail the specific internal RC-inverter triggering topology claimed.
Youssef lacks the specific topology of a resistor, capacitor, P-type FET, and two N-type FETs configured as a single-stage inverter-driven clamp.
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Fig. 8A of Yeh reproduced for ease of reference.
While Stockinger teaches a distributed clamp, it uses multiple inverter stages. However, Yeh (US 20100149703, cited by the applicant) teaches the exact claimed single-inverter RC trigger topology. Figure 8A of Yeh shows an ESD clamp circuit 710 comprising a resistor 801 coupled to the voltage source 711 and a first node, and a capacitor 802 coupled to the reference 712 and the first node. It shows a P-type FET 803 and a first N-type FET 804 with their gates coupled to the first node and their channels coupled between the voltage source 711 and reference 712, outputting to a second internal node. It further shows a second N-type FET 717 (the main clamp) coupled between the voltage source and reference, with its gate coupled to the second internal node.
It would have been obvious to a PHOSITA to implement the distributed ESD clamps of Stockinger using the specific, compact RC-inverter trigger circuit taught by Yeh.
The motivation to use the specific RC-inverter topology of Yeh within the distributed clamp network is to provide a reliable transient-triggered ESD clamp that reacts quickly to fast-rising voltage spikes (via the RC time constant) while minimizing layout area by employing a highly efficient single-stage inverter to drive the main clamp FET.
Regarding Claims 5, 11, and 17 (Filter Capacitor)
Youssef teaches an integrated RF circuit but does not explicitly show a filter capacitor coupled directly between the voltage source terminal and the reference potential.
Youssef misses the explicit illustration of the filter (bypass/decoupling) capacitor on the supply rail.
It is a universally known and standard engineering practice (Official Notice) to place a filter capacitor (also known as a bypass or decoupling capacitor) between a voltage source terminal (VDD) and a reference potential (GND) for integrated RF circuits to stabilize the power supply.
It would have been obvious to a PHOSITA to add a filter capacitor between the voltage source terminal and the reference potential in the combined multi-LNA architecture of Youssef/Kasha/Stockinger.
The motivation for adding a filter capacitor across the supply rails is to decouple AC noise, stabilize the DC supply voltage during high-frequency operation, and prevent RF signal leakage into the power supply network, which is fundamentally required to ensure proper LNA performance.
Regarding Claims 6, 12, and 18 (Output Clamp)
Youssef focuses on input and supply clamps but does not explicitly detail an output clamp coupled between the output terminal and the reference potential.
Youssef misses the output clamp to the reference potential.
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Fig. 6 of Seshita reproduced for ease of reference.
Seshita (US 20200403580) teaches an RF LNA that incorporates a clamp circuitry 14 connected directly between the drain of the first transistor (which acts as the output node of that amplifier stage) and the ground potential (reference potential).
It would have been obvious to a PHOSITA to modify the amplifier cores of the combined Youssef/Kasha/Stockinger architecture to include an output clamp coupled between the output terminal and the reference potential, exactly as taught by Seshita.
The motivation to add the output clamp to the reference potential is to improve excessive input resistance and protect the internal nodes of the amplifier (specifically the drain/output) from transient voltage spikes and secondary ESD events that might bypass the primary input protections.
Allowable Subject Matter
Claims 13 and 19 are objected to as being dependent upon a rejected base claim 7 and 14 respectively but would be allowable if rewritten to overcome the obviousness double patenting rejection and in independent form including all the limitations of the base claim and any intervening claims.
Claims 13 and 19 require "a clamp diode coupled between the voltage source terminal and the amplified-signal port." The amplified-signal port represents an internal high-frequency output node of the amplifier core (e.g., the drain). While the prior art teaches clamping the drain to the gate (e.g., Youssef’s DP4) or clamping the drain to ground (e.g., clamp 14, Fig. 6 of Seshita et al., US 2020/0403580 A1), none of the cited references teach placing a clamp diode specifically between the amplified-signal port and the voltage source terminal (VDD). Furthermore, introducing a diode between a high-frequency amplified RF node and the VDD rail would introduce unwanted parasitic junction capacitance, severely degrading the LNA's high-frequency gain and matching. Because the prior art does not teach this limitation and actively teaches away from adding unnecessary parasitics to VDD from sensitive RF output nodes, claims 13 and 19 are allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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