DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim 1 recites “the lower conductive”, which lacks antecedent basis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 7, 8, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the lower conductive ,” which lacks antecedent basis.
Claim 7 recites “a portion an upper surface the substrate defines a direct contact hole”. This phrase is not parsable or understandable. It appears that the applicant perhaps intends “a portion of an upper surface of the substrate defines a direct contact hole”.
Claim 8 has the same problem.
Claim 11 recites “a metal oxide layer on one of sidewalls of the upper conductive layer and the intermediate conductive layer.” The metal oxide layers are addressed in the specification at [0092]-[0096]; the specification states that “the first metal oxide layer 146 may be a titanium metal nitride layer or a titanium silicon nitride oxide layer.” It is clear that the scope of the claimed metal oxide layer is not limited to oxides of metal, which titanium nitride is not. There is no indication in the specification as to what the scope of this term is.
Claim 19 recites that “one sidewall of the depletion stopping layer is located on an inner side relative to one sidewalls of the intermediate conductive layer and the upper conductive layer in the first horizontal direction.” It is not clear what “located on an inner side relative to one sidewalls of the intermediate conductive layer and the upper conductive layer” means. An inner side of what? For present purposes, the examiner will assume that this means an inner side of any of the spacer layers.
The remaining claims are rejected based on their dependencies.
Claim 11 has not been rejected over the prior art because, in light of the 35 U.S.C. 112 rejections supra, there is sufficient uncertainty that it would not be proper to reject the claims on the basis of prior art. As stated in In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee, US 2013/0320549 A1.
Claim 1: Lee discloses
a substrate (201);
a word line (BG) extending on the substrate in a first horizontal direction (horizontal, FIG. 3A);
a bit line (208) extending on the substrate in a second horizontal direction (vertical, FIG. 3A) perpendicular to the first horizontal direction;
and a spacer structure (213) on one sidewall of the bit line,
wherein the bit line includes a lower conductive layer (208), an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes,
a depletion stopping layer (210) on one sidewall of the lower conductive , extending in the vertical direction, and including a material layer (silicon oxide, [0051]) having an interfacial trap density less than an interfacial trap density of a silicon nitride layer,
and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.
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Claims 1-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hong, US 2021/0398569 A1.
Claim 1: Hong discloses
a substrate (110);
a word line (118) extending on the substrate in a first horizontal direction (horizontal, FIG. 1);
a bit line (BL) extending on the substrate in a second horizontal direction (vertical, FIG. 1) perpendicular to the first horizontal direction;
and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer (130), an intermediate conductive layer (132), and an upper conductive layer (134) stacked in a vertical direction on the substrate, and the spacer structure includes,
a depletion stopping layer (140) on one sidewall of the lower conductive , extending in the vertical direction, and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer (silicon oxide, [0038]), and an inner spacer (142) extending in the vertical direction and on one sidewall of the depletion stopping layer.
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Claim 2: the lower conductive layer includes a polysilicon layer doped with impurities ([0031]), and the depletion stopping layer includes a silicon oxide layer ([0038]).
Claim 3: the inner spacer includes a silicon oxide layer or a carbon-containing oxide layer ([0035]).
Claim 4: Hong discloses at [0031] that “the intermediate conductive layer 132 may include a TiN layer and/or a TiSiN layer, and the upper conductive layer 134 may include a layer including Ti, TiN, W, WN, WSixNy, Ru, or a combination thereof. The insulating capping pattern 136 may include a silicon nitride layer.” Those in the art would recognize the materials of layer 132 as barrier materials, and they are disclosed as such in the present application ([0065]-[0067]).
Claim 5: the spacer structure includes: an intermediate spacer (146) on one sidewall of the inner spacer and extending in the vertical direction; and an outer spacer (148) on one sidewall of the intermediate spacer and extending in the vertical direction.
Claim 6: the intermediate spacer includes a silicon oxide layer ([0047]), and the outer spacer includes a silicon nitride layer ([0049]).
Claim 7: a portion an upper surface the substrate defines a direct contact hole (DCH), the substrate further includes an active region (ACT) in the direct contact hole, the bit line contacts the active region in the direct contact hole, and a gap-fill insulating pattern (144) in the direct contact hole and on one sidewall of the space structure. Hong discloses at [0029] that “[e]ach of the plurality of bit lines BL may be connected to the active region ACT via the direct contact DC.” Thus the bit lines make electrical contact with the active region in the direct contact hole.
Claim 8: a portion an upper surface the substrate defines a buried contact hole (BC), the substrate further includes an active region (ACT) in the buried contact hole, and a buried contact plug (150, [0136]) is in contact with the active region in the buried contact hole.
Claim 9: Hong discloses
a substrate (11o);
a word line (118) extending on the substrate in a first horizontal direction (horizontal, FIG. 1);
a bit line (BL) extending on the substrate in a second horizontal direction (vertical, FIG. 1) perpendicular to the first horizontal direction;
and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer (130), an intermediate conductive layer (132), and an upper conductive layer (134) stacked in a vertical direction on the substrate,
and the spacer structure includes,
a depletion stopping layer (140) on one sidewall of the lower conductive layer, extending in the vertical direction, and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer,
a passivation layer (142) extending in the vertical direction and on a portion of one sidewall of the upper conductive layer,
and an inner spacer (146) on one sidewall of the passivation layer and on one sidewall of the depletion stopping layer, and extending in the vertical direction.
Claim 10: the inner spacer is continuously on an upper portion of one sidewall of the bit line (FIG. 2B).
Claim 12: the passivation layer is further on one sidewall of an upper portion of the lower conductive layer and one sidewall of the intermediate conductive layer (FIG. 2B).
Claim 13: the spacer structure includes: an intermediate spacer (148) on one sidewall of the inner spacer and extending in the vertical direction; and an outer spacer (149) on one sidewall of the intermediate spacer and extending in the vertical direction.
Claim 14: the substrate includes a cell center region and a cell edge region surrounding the cell center region when viewed in a plan view, and the passivation layer is on at least one sidewall of the intermediate conductive layer or the upper conductive layer of the bit line in the cell edge region. The passivation layer is disclosed as on the sidewall of the intermediate conductive layer and the upper conductive layer in the cells, which would suggest in all the cell regions.
Claim 15: the substrate includes a cell center region and a cell edge region surrounding the cell center region when view in a plan view, and the passivation layer is on one sidewall of the upper conductive layer of the bit line in the cell edge region. The passivation layer is disclosed as on the sidewall of the upper conductive layer in the cells, which would suggest in all the cell regions.
Claim 17: Hong discloses
a substrate (11o);
a word line (118) extending on the substrate in a first horizontal direction (horizontal, FIG. 1);
a bit line (BL) extending on the substrate in a second horizontal direction (vertical, FIG. 1) perpendicular to the first horizontal direction;
and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer (130), an intermediate conductive layer (132), and an upper conductive layer (134) stacked in a vertical direction on the substrate,
and the spacer structure includes,
a depletion stopping layer (140) on one sidewall of the lower conductive layer, extending in the vertical direction, and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer,
an inner spacer (146) extending in the vertical direction and on one sidewall of the depletion stopping layer,
and a passivation layer (142) extending in the vertical direction and on one sidewall of the inner spacer, one sidewall of the intermediate conductive layer, and one sidewall of the upper conductive layer.
Claim 18: the passivation layer extends nonlinearly in the vertical direction (it has a jog in its vertical extent).
Claim 19 one sidewall of the depletion stopping layer is located on an inner side relative to one sidewalls of the intermediate conductive layer and the upper conductive layer in the first horizontal direction (FIG. 2A). 19. The sidewall of the depletion stopping layer is on an inner side of the spacer layers 142 and 144.
Claim 20: the spacer structure includes: an intermediate spacer (148) on one sidewall of the passivation layer and extending in the vertical direction; and an outer spacer (149) on one sidewall of the intermediate spacer and extending in the vertical direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2017/0005097 A1 (Kim 1), in view of Kim, US 2022/0085026 A1 (Kim 2).
Claim 1: Kim 1 discloses
a substrate (100);
a word line (WL) extending on the substrate in a first horizontal direction;
a bit line (BL) extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction;
and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate,
and the spacer structure includes,
a depletion stopping layer (121) on one sidewall of the lower conductive , extending in the vertical direction, and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer (silicon oxycarbonitride, [0058]), and an inner spacer (122 and/or 123) extending in the vertical direction and on one sidewall of the depletion stopping layer.
Kim 1 discloses two bit line conductive layers, rather than the three recited in claim 1. However, this was known in the art. See e.g. Kim 2, FIG. 2, wherein the bit line includes a lower conductive layer (265), an intermediate conductive layer (325), and an upper conductive layer (305) stacked in a vertical direction on the substrate. It would have been obvious to have had such an arrangement as known in the art, and also in order include a diffusion barrier (Kim 2, 295, [0027]) in order to prevent diffusion into the polysilicon lower conductive layer of Kim 1.
The semiconductor device of claim 1, wherein the lower conductive layer includes a polysilicon layer doped with impurities (Kim 2, [0126]), and the depletion stopping layer includes a silicon oxide layer.
Claim 3: the inner spacer includes a silicon oxide layer or a carbon-containing oxide layer (Kim 1, [0058]).
Claim 4: the intermediate conductive layer includes a barrier metal layer barrier (Kim 2, [0027]), and the upper conductive layer includes a metal layer ([0027]).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The examiner did not find the claimed passivation layer on the claimed insulating pattern in the matter recited in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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