DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 2 and Subspecies 3 (fig. 5C) directed to claims 1-6 and 10-20 in the reply filed on 12/15/2025 is acknowledged. The traversal is on the ground(s) that “the subject matter in the listed species and subspecies is sufficiently related such that a search for the subject matter of any one of these species and subspecies would encompass a search for the subject matter of the remaining species and subspecies. Accordingly, there would be no need to search in separate fields, and thus examining all of the species and subspecies would not be burdensome of the Examiner. See MPEP 803, 808, and 808.02” [REMARKS page 2]. This is not found persuasive because each species and subspecies listed in the restriction dated 11/17/2025 will require unique searches for the distinct structural elements, a search of one specie will not overlap with that of the other species and therefore will create a search burden.
Therefore the requirement is still deemed proper and is therefore made FINAL.
Claims 7-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 states, “in the top view, the second dielectric is separated from the first metal by the third dielectric”. It is unclear the relationship between the “first metal” which is within the first build-up circuit layer and the “third dielectric” which is adjacent to the “second metal” and found within the second build-up circuit layer. Applicants’ specification repeats this feature in paragraph 0009 but there are no drawing and no further explanation outside of what is currently claimed. For the purpose of examination the “second metal” will be considered. There may be some superimposed feature the Applicant intends to claim but as the claim is currently written it cannot be determined and further amendment is required to determine the meets and bounds of the limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 10, 15, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tay et al. (US PG. Pub. 2023/0217589).
Regarding claim 1 – Tay teaches a wiring board structure (fig. 1B & 5), comprising: a substrate (C [paragraph 0090] Tay states, “core C”) having a first side (top surface) and a second side (bottom surface) opposite to each other; a first build-up circuit layer (upper stack having layers L1-L4 & D1-D3) disposed on the first side (top surface) of the substrate (C), wherein the first build-up circuit layer has a first wiring area (L1-L4 [paragraph 0094] Tay states, “electrically conductive layers L1, L2, L3, L4”), and the first wiring area comprises: a first metal (L1); a first dielectric (D1); and a second build-up circuit layer (lower stack having layers L1’-L3’ & D1’-D3’) disposed on the second side (bottom side) of the substrate (C), wherein the second build-up circuit layer has a second wiring area (L1’-L3’ [paragraph 0107] Tay states, “copper layer structure L1’-L4’ ”), and the second wiring area comprises: a second metal (L1’), wherein a total volume ([paragraph 0101] Tay states, “FIG. 5 shows a schematic representation of a component carrier having an asymmetric 3-2-2”; figures 1B and 5 show additional copper in the first build-up circuit layer than in the second build-up circuit layer and appears to meet the “total volume” claim language) of the second metal (L1’-L3’) is less than a total volume of the first metal (L1-L4); a second dielectric (D1’); and a third dielectric (D2’), wherein a material of the third dielectric (D2’) is different from a material of the second dielectric (D1’ [Claim 1] Tay states, “each one of these at least two second electrically insulating layer structures has a smaller thickness than and/or comprises a different material property than at least one of the first electrically insulating layer structures”), and a ratio of a total volume (D2’ layer having a volume of 1X) of the third dielectric (D2’) to a total volume (D1’ layer having a volume of 2X) of the second dielectric (D1’) is between 0.45 and 0.55 (total volume of 3rd dielectric = 1X, total volume of 2nd dielectric = 2X; 1X/2X = 0.5).
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Regarding claim 3 – Tay teaches the wiring board structure as claimed in claim 1, wherein in a top view, the second wiring area (figs. 1B & 5, L1’-L3’) has two opposite straight sides and two opposite arc sides (the second wiring area can be selected to have this particular shape as the area will be user defined).
Regarding claim 10 – Tay teaches the wiring board structure as claimed in claim 1, wherein the third dielectric (figs. 1B & 5, D2’) penetrates the second build-up circuit layer (lower stack having layers L1’-L3’ & D1’-D3’) along a vertical direction (D2’ is shown to be within the second build-up circuit layer in the vertical direction).
Regarding claim 15 – Tay teaches the wiring board structure as claimed in claim 1, wherein a material ([paragraph 0033] Tay states, “whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material”) of the first dielectric (fig. 1B & 5, D1) is the same as a material of the second dielectric (D1’; D1 and D1’ are considered to be the same material).
Regarding claim 18 – Tay teaches the wiring board structure as claimed in claim 1, wherein a material of the first metal (figs. 1B & 5; L1) is the same as a material of the second metal (L1’; both are shown to be copper in the respective figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. in view of Shimizu et al. (US PG. Pub. 2015/0245473).
Regarding claim 2 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein the first wiring area and the second wiring area correspond to each other, and a volume of the first wiring area is the same as a volume of the second wiring area.
Shimizu teaches a wiring board structure (fig. 1, 10) wherein the first wiring area (wiring area including wiring layers 50, 52, 54 and 56) and the second wiring area (wiring area including wiring layers 46) correspond to each other (areas shown on opposite sides of the core layer 20), and a volume of the first wiring area is the same as a volume of the second wiring area ([paragraph 0069] Shimizu states, “a ratio V1/V2 of the volume V1 of the wiring layers 50, 52, 54, and 56 relative to the volume V2 of the bottom wiring layer 46 is preferably from 0.8 to 1.5”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a first and second wiring area as taught by Tay with the first and second wiring areas having the same volume as taught by Shimizu because Shimizu states, “Setting the volume ratio V1/V2 in this way makes it possible to reduce the amount of warp of the wiring substrate 10 more appropriately” [paragraph 0069].
Claim(s) 4-5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. as applied to claims 1 and 3 above, and further in view of Kim et al. (US PG. Pub. 2005/0178585).
Regarding claim 4 – Tay teaches the wiring board structure as claimed in claim 3, but fails to teach wherein in the top view, the third dielectric surrounds the second metal and is in direct contact with the second metal.
Kim teaches wherein in the top view, the third dielectric (figs. 5a-5b, 443 [paragraph 0055] Kim states, “insulating material 443”) surrounds the second metal (441 [paragraph 0054 & claim 4] Kim states, “via holes 441a, 441b…via hole is a copper plating layer”) and is in direct contact with the second metal (claimed structure shown in figures 5a and 5b).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a third dielectric and a second metal as taught by Tay with the third dielectric surrounding the second metal and in contact with the second metal as taught by Kim because Kim states, “an insulating material 443 be packed between the two holes so as to prevent the outer ground via hole 442 from being shorted with the two inner via holes 441a, 441b. Therefore, the outer ground via hole 442 and the two inner via holes 441a, 441b can independently transfer signals therethrough.” [paragraph 0055].
Regarding claim 5 – Tay in view of Kim teaches the wiring board structure as claimed in claim 4, wherein in the top view the second dielectric (Kim; figs. 5a-5b, dielectric material shown between conductors 421 & 422) is separated from the second metal (441a & 441b) by the third dielectric (443).
Regarding claim 19 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein the second metal forms a plurality of vertical connectors, and the plurality of vertical connectors are electrically isolated from each other.
Kim teaches wherein the second metal forms a plurality of vertical connectors (fig. 5a-5b, 441a & 441b [paragraph 0054 & claim 4] Kim states, “via holes 441a, 441b…via hole is a copper plating layer”), and the plurality of vertical connectors (441a & 441b) are electrically isolated from each other (claimed structure shown in figures 5a and 5b).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a third dielectric and a second metal as taught by Tay with the second metal forms a plurality of vertical conductors that are electrically isolated from each other as taught by Kim because Kim states, “an insulating material 443 be packed between the two holes so as to prevent the outer ground via hole 442 from being shorted with the two inner via holes 441a, 441b. Therefore, the outer ground via hole 442 and the two inner via holes 441a, 441b can independently transfer signals therethrough.” [paragraph 0055].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. in view of Silvano de Sousa et al. (US PG. Pub. 2019/0174638).
Regarding claim 11 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein a Young's modulus of the third dielectric material is greater than 1000 MPa at 250°C.
Silvano teaches a third dielectric material (fig. 6, 112) wherein a Young's modulus of the third dielectric material is greater than 1000 MPa at 250°C ([paragraph 0109] Silvano states, “the electrically insulating layer structures 112 should be made of a material having a low value of the Young modulus (preferably less than 10 GPa at 250° C.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a third dielectric material as taught by Tay with the third dielectric material having a Young’s modulus of the third dielectric material greater than 1000MPa at 250°C as taught by Silvano because Silvano states, “A sufficiently soft dielectric material reduces stress and prevents undesired delamination” [paragraph 0109].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. in view of Silvano de Sousa et al. as applied to claim 11 above, and further Sugawara et al. (US PG. Pub. 2022/0169791).
Regarding claim 12 – Tay in view of Silvano teach the wiring board structure as claimed in claim 1, but fails to teach wherein a Young's modulus of the third dielectric material is between 1800MPa and 2400MPa at 250°C.
Sugawara teaches a third dielectric material ([TABLE 2] Sugawara states, “polyimide resin”) wherein a Young's modulus of the third dielectric material is between 1800MPa and 2400MPa ([TABLE 2] Sugawara states, “Elastic modulus Mpa 2210”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a third dielectric material with a Young’s Modulus greater than 1000MPa at 250°C
as taught by Tay in view of Silvano with the third dielectric material having a Young’s modulus of the third dielectric material between 1800MPa and 2400MPa as taught by Sugawara because Sugawara states regarding this material and its properties, “a resin composition that contains this resin material and has a cured product thereof having a low dielectric loss tangent and excellent adhesion, heat resistance, and mechanical characteristics” [Abstract].
Claim(s) 13-14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. in view of Amla et al. (US Patent 11596066).
Regarding claim 13 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein a thermal expansion coefficient of the third dielectric is greater than 70 ppm/°C at 250°C.
Amla teaches wherein a thermal expansion coefficient of the third dielectric is greater than 70 ppm/°C at 250°C ([column 10 lines 6-10] Amla states, “the coefficient of thermal expansion (CTE) of the dielectric material from 50 to 250° C. is up to about 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 or 300 ppm/° C”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having a third dielectric as taught by Tay with the third dielectric having a CTE greater than 70 ppm/°C at 250°C as taught by Amla because Amla states, “the dielectric layer reduces the risk of failure of the one or more microvias due to low cycle fatigue or overstress, as compared to when the dielectric layer is absent from the high-density interconnect printed circuit board.” [column 5 lines 25-29].
Regarding claim 14 – Tay teaches the wiring board structure as claimed in claim 13, but fails to teach wherein thermal expansion coefficients of the third dielectric is between 75 ppm/°C and 95 ppm/°C at 250°C.
Amla teaches wherein thermal expansion coefficients of the third dielectric is between 75 ppm/°C and 95 ppm/°C at 250°C ([column 10 lines 6-10] Amla states, “the coefficient of thermal expansion (CTE) of the dielectric material from 50 to 250° C. is up to about 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 or 300 ppm/° C”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having the first and second dielectric as taught by Tay with the first and second dielectric having CTE of between 75-95 ppm/°C at 250°C as taught by Amla because Amla states, “the dielectric layer reduces the risk of failure of the one or more microvias due to low cycle fatigue or overstress, as compared to when the dielectric layer is absent from the high-density interconnect printed circuit board.” [column 5 lines 25-29].
Regarding claim 17 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein thermal expansion coefficients of the first dielectric and the second dielectric are between 40 ppm/°C and 60 ppm/°C at 250°C.
Amla teaches wherein thermal expansion coefficients of a dielectric is between 40 ppm/°C and 60 ppm/°C at 250°C ([column 10 lines 6-10] Amla states, “the coefficient of thermal expansion (CTE) of the dielectric material from 50 to 250° C. is up to about 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 or 300 ppm/° C”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having the first and second dielectric as taught by Tay with the first and second dielectric having CTE of between 40-60 ppm/°C at 250°C as taught by Amla because Amla states, “the dielectric layer reduces the risk of failure of the one or more microvias due to low cycle fatigue or overstress, as compared to when the dielectric layer is absent from the high-density interconnect printed circuit board.” [column 5 lines 25-29].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tay et al. in view of Eda et al. (US PG. Pub. 2023/0235229).
Regarding claim 16 – Tay teaches the wiring board structure as claimed in claim 1, but fails to teach wherein a Young's modulus of the first dielectric and the second dielectric is between 100MPa and 500MPa at 250°C.
Eda teaches wherein a Young's modulus of the first dielectric (fig. 3, 1B [paragraph 0034] Eda states, “liquid crystal polymer film 1”) and the second dielectric (1C) is between 100MPa and 500MPa at 250°C ([paragraph 0034] Eda states, “a lower storage elastic modulus, for example, of 500 MPa or less at 250° C”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board structure having the first and second dielectric as taught by Tay with the first and second dielectric having a Young’s modulus between 100 MPa and 500 MPa at 250°C as taught by Eda because Eda states, “in multilayer substrates with an interlayer connection conductor produced from these liquid crystal polymer films, it is thought that the interlayer connection conductor is less likely to have a crack and is consequently less likely to have lower connection reliability” [paragraph 0227].
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
S et al. (US PG. Pub. 2022/0201836) discloses a multi-dielectric printed circuit board.
Jiang et al. (US Patent 9401330) discloses an IC package with non-uniform dielectric layer thickness.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847