DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1 has been cancelled.
Claim Rejections - 35 USC § 112
Claim(s) 3, 5, 7, 11, 13 and 21 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is claimed, in claim 3: “wherein performing the second access operation comprises: performing the second access operation after completion of the first access operation.” (emphasis added) It is unclear, leading to distinctly different interpretations, whether, as claimed, there is a complementary second access operation that follows a primary second access operation. The claim could be redacted alternatively to remove alternative interpretations, and thus distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. An alternative claim construct, if indeed this is what is meant to be claimed -otherwise this is meaningless- could be: The method of claim 2, wherein after completion of the first access operation, performing the second access operation.
While in regard to claim 5, in similitude to the rejection to claim 3, claim 5 includes, in part: “the method further comprising: performing the precharge operation after performing the precharge operation before performing the second access operation.” It is unknowable whether the precharge after the precharge are two distinctly different operations, or are the same, or any other interpretation.
While in regard to claim 7, it includes: “wherein the plurality of bits are associated with a read auto precharge plus refresh command or a write auto precharge plus refresh command.” (emphasis added) The term “associated” is vague and doesn't clearly define the scope of the invention; it lacks precision, clarity, and distinctness preventing a skilled person from understanding what is being claimed, what interpretation it should be given to, and the scope of potential infringement. How are the bits “associated” with the operation? In sum, the claim as a whole is indefinite.
While in regard to claim 11, in similitude: “perform the precharge operation after performing the precharge operation before performing the second access operation” is found indefinite, making the claim as a whole indefinite.
While in regard to claim 13, in similitude with claim 7, The term “associated” is vague and doesn't clearly define the scope of the invention; it lacks precision, clarity, and distinctness preventing a skilled person from understanding what is being claimed, what interpretation it should be given to, and the scope of potential infringement. How are the bits “associated” with the operation? In sum, the claim as a whole is indefinite.
While in regard to claim 21, in similitude with claim 7, The term “associated” is vague and doesn't clearly define the scope of the invention; it lacks precision, clarity, and distinctness preventing a skilled person from understanding what is being claimed, what interpretation it should be given to, and the scope of potential infringement. How are the bits “associated” with the operation? In sum, the claim as a whole is indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”).
As to claim 2, Kwon teaches substantially the claimed invention, including, but not limited to: a method at a memory device (As found in the methodology of operating a memory device in at least the Abstract), comprising: receiving, via a plurality of command/address terminals of the memory device, a plurality of bits including a first set of bits that instruct the memory device to perform a first access operation on a portion of a memory array of the memory device (As found in at least FIGS. 1-2 and at least [0013], [0041], [0056], [0057], [0062]: memory device 100 receives first command/address/data from 200; the methodology including, for one, read or write operation commands/address) and a second set of bits that instruct the memory device to perform a second access operation on the portion of the memory array (As found in at least [0057]: second set of command/address to perform second operation such as program verify).
While Kwon evidently teaches first and second memory operations upon receiving command/address/data, Kwon may not expressly teach that the portion of memory for the first and second access operations are the same; that is, as claimed: performing the first access operation on the portion of the memory array in response to receiving the first set of bits; and performing the second access operation on the portion of the memory array in response to receiving the second set of bits.
However, Takano evidently teaches that the portion of memory for the first and second access operations are the same; that is, as claimed: performing the first access operation on the portion of the memory array in response to receiving the first set of bits; and performing the second access operation on the portion of the memory array in response to receiving the second set of bits (As found in at least FIG. 2: first and second access operations, such as READ and WRITE, can be performed on the same portion of memory array, as given by command/address bit information: /CS, /WE, /REF/, Add(20) and BA(3); moreover, Takano in at least FIG. 4 also teaches receiving at terminals of a memory device command/address bits, ADD, BA, /CS, /WE, /REF for the operation of such memory device).
Kwon and Takano are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device operations based on command/address information.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kwon as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Takano also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: both Kwon and Takano provide teachings that commonly address memory device operations that can include first and second operations based on command/address information received by the memory device; Takano makes explicit the use of received command/address information that is used by the memory device in performing any number of operations.
Therefore, it would have been obvious to combine Kwon with Takano to make the above modification.
As to claim 4, both Kwon and Takano teach wherein performing the first access operation comprises: performing a read operation on the portion of the memory array or a write operation on the portion of the memory array (As found in at least [0041] in Kwon, and as found in at least FIG. 2 in Takano).
As to claim 6, at least Takano teaches wherein performing the second access operation comprises: performing a refresh operation on the portion of the memory array (As found in at least FIG. 2, a second access operation, other than, for example, read and/or write, can be a refresh operation (REFRESH)).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”), and further in view of US 20180314635 to Alam (“Alam”).
As to claim 7, while Kwon as modified teaches the claimed command, the teachings may not expressly include wherein the plurality of bits are associated with a read auto precharge plus refresh command or a write auto precharge plus refresh command.
Yet, relevantly and complementarily, Alam teaches wherein the plurality of bits are associated with a read auto precharge plus refresh command or a write auto precharge plus refresh command (As found in at least [0035]: “an external memory controller can provide commands 434 to the control circuitry 450 where such commands include activate, read, write, precharge, read with autoprecharge, write with autoprecharge, and refresh commands).
Kwon as modified and Alam are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device operations based on command/address information.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kwon as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Alam also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: both Kwon and Takano provide teachings that commonly address memory device operations that can include first and second operations based on command/address information received by the memory device; Takano makes explicit the use of received command/address information that is used by the memory device in performing any number of operations. While Alam further complements these teachings by introducing, advantageously, memory commands that may include a number of operations, all one after another
Therefore, it would have been obvious to combine Kwon as modified with Alam to make the above modification.
Claim(s) 8, 9, 14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”), and further in view of US 20190369915 to Prather et al. (“Prather”).
As to claim 8, see rejection to at least claim 1; moreover, Kwon, Takano and Prather evidently teach: one or more circuits configured to: receive, via the plurality of command/address terminals (As found in at least FIGS. 1-2 in Kwon: 120; as found in at least FIGS. 1, 4 in Takano: 1, 2, 3; as found in at least FIG. 1 in Prather: 105); additionally, at least Prather evidently teaches: the one or more circuits configured to receive the first set of bits and the second set of bits at the same time or in a single communication (As found in at least FIG. 1: single communication over CMD includes: “a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read,” as found in the Abstract, and at least [0010]).
Kwon as modified and Prather are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device operations based on command/address information.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kwon as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Prather also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: while Kwon and Takano teach commands that may include information to perform first and second memory access operations, Prather further these teachings by including evidence of a single command that includes first and second information that leads to the operation of first and second memory access operations; this single command for first and second operations is advantageous: any memory access command requires the expenditure of electrical current; multiple commands requiring multiple such expenditures, while a single command requiring advantageously less current.
Therefore, it would have been obvious to combine Kwon as modified with Prather to make the above modification.
As to claim 9, Prather teaches wherein the one or more circuits are configured to: perform the second access operation after completion of the first access operation (As found in the rejection to claim 8; also, as found in the Abstract and at least [0010]).
As to claim 14, Kwon teaches included in a single memory die (As found in at least [0147]: memory device 100 in a Die).
As to claim 16, see rejection to at least claim 8; moreover, at least Kwon teaches a memory controller, configured to: transmit, to a plurality of command/address terminals of a memory device via a command/address bus (As found in at least FIG. 1: controller 200 transmits command/address/data to memory 100 via a bus).
As to claim 17, see rejection to at least claim 9.
Claim(s) 13 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”), and further in view of US 20190369915 to Prather et al. (“Prather”), and further in view of US 20180314635 to Alam (“Alam”).
As to claim(s) 13 and 21, see rejection to at least claim 7. As in the rejection to claim 7, the teachings of Alam further complements these teachings by introducing, advantageously, memory commands that may include a number of operations, all one after another
Therefore, it would have been obvious to combine Kwon as modified with Alam to make the above modification.
Claim(s) 10, 15, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”), and further in view of US 20190369915 to Prather et al. (“Prather”), and further in view of US 20220050794 to Lin et al. (“Lin”).
As to claim 10, while Kwon as modified teaches first and second access operations in a single communication, Kwon as modified may not expressly teach wherein the first access operation comprises a read operation on the portion of the memory array or a write operation on the portion of the memory array.
Yet, relevantly and complementarily, Lin teaches wherein the first access operation comprises a read operation on the portion of the memory array or a write operation on the portion of the memory array (As found in at least FIG. 7 and [0004]: “In one exemplary implementation, a write with auto-precharge (WRA) or read with auto precharge (RDA) is used instead of a respective write command (WR) and read command (RD)… The memory controller can use a read/write with auto-precharge command to preserve a slot on the command bus for use by another access command”).
Kwon as modified and Lin are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device operations based on command/address information.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kwon as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lin also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: while Kwon and Takano teach commands that may include information to perform first and second memory access operations, Prather further these teachings by including evidence of a single command that includes first and second information that leads to the operation of first and second memory access operations; this single command for first and second operations is advantageous: any memory access command requires the expenditure of electrical current; multiple commands requiring multiple such expenditures, while a single command requiring advantageously less current; and moreover, Lin complements these teachings by evidently including a read and/or write access operation as the first access operation.
Therefore, it would have been obvious to combine Kwon as modified with Lin to make the above modification.
As to claim 15, at least Lin teaches included in multiple memory dies (As found in at least [0036]).
As to claim 18, see rejection to at least claim 10.
As to claim 19, see rejection to at least claim 10: As found in at least FIG. 7 and [0004]: “In one exemplary implementation, a write with auto-precharge (WRA) or read with auto precharge (RDA).
Claim(s) 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220083253 to Kwon et al. (“kwon”) in view of U.S. Patent/Publication No. 20110007593 to Takano (“Takano”), and further in view of US 20190369915 to Prather et al. (“Prather”), and further in view of US 20180114580 to Alrod et al. (“Alrod”).
As to claim 12, at least Alrod teaches wherein the second access operation comprises a refresh operation on the portion of the memory array (As found in at least [0216], [0229]: a read refresh memory access operation).
Kwon as modified and Alrod are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory device operations based on command/address information.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kwon as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Alrod also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: while Kwon and Takano teach commands that may include information to perform first and second memory access operations, Prather further these teachings by including evidence of a single command that includes first and second information that leads to the operation of first and second memory access operations; this single command for first and second operations is advantageous: any memory access command requires the expenditure of electrical current; multiple commands requiring multiple such expenditures, while a single command requiring advantageously less current; and moreover, Lin complements these teachings by evidently including a read refresh memory access operation.
Therefore, it would have been obvious to combine Kwon as modified with Alrod to make the above modification.
As to claim 20, see rejection to at least claim 12.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
At least Claim(s) 2, 8 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim(s) 1, 10 and 17 of U.S. Patent No. 11409674. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are obviated by the patented claims. A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over (in a non-statutory double patent rejection) the earlier claim. In re Lonqi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Bercl, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). Ely Lilly and Co. v Bar Laboratories, Inc., United States Court of Appeals for the Federal Circuit, on petition for rehearing en banc (decided: May 30, 2001).The instant claims are obviated by the patented claims; the patent and the application claim obvious common subject matter; in brief and saliently: memory device and/or method thereof, comprising, in brief and saliently: receiving, via a plurality of command/address terminals of the memory device, a plurality of bits including a first set of bits that instruct the memory device to perform a first access operation on a portion of a memory array of the memory device and a second set of bits that instruct the memory device to perform a second access operation on the portion of the memory array; performing or executing the first access operation on the portion of the memory array in response to receiving the first set of bits; and performing or executing the second access operation on the portion of the memory array in response to receiving the second set of bits. Moreover, at least claims 8 and 16 of the present Application further require, in brief and saliently: receive the first set of bits and the second set of bits at the same time or in a single communication. While the claims of the Patent obviate this claim requirement: configured to receive a single command as a corresponding plurality of bits; where the command, as claimed, includes first and second subset of bits.
In similitude, at least claim(s) 2, 8 and 16 of the present Application are rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim(s) 1, 2, 11, 15 and 19 of U.S. Patent No. 11934326. The instant claims are obviated by the patented claims; the patent and the application claim obvious common subject matter; in brief and saliently: memory device and/or method thereof, comprising, in brief and saliently: receiving, via a plurality of command/address terminals of the memory device, a plurality of bits including a first set of bits that instruct the memory device to perform a first access operation on a portion of a memory array of the memory device and a second set of bits that instruct the memory device to perform a second access operation on the portion of the memory array; performing or executing the first access operation on the portion of the memory array in response to receiving the first set of bits; and performing or executing the second access operation on the portion of the memory array in response to receiving the second set of bits. Moreover, at least claims 8 and 16 of the present Application further require, in brief and saliently: receive the first set of bits and the second set of bits at the same time or in a single communication. While claims 2 and 19 of the Patent obviate this claim requirement: configured to receive a single command as a corresponding plurality of bits; where the command, as claimed, includes first and second subset of bits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827