DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the list of items below must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1: “wherein the second die is directly bonded to the second surface of the redistribution layer”.
Per Fig. 4A, the second die 245 is bonded to the RDL via element 250 (“soldering of the components on to the RDL (using SOP (Solder on Pad), Cu-pillar (copper pillar), or solder bump technologies 250)”); direct bonding is not shown. Furthermore, claim 1 is drawn to Fig. 4A given the requirement of an RDL; claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
Claim 11: “directly bonding a second die to the second surface of the redistribution layer”.
Per Fig. 4A, the second die 245 is bonded to the RDL via element 250 (“soldering of the components on to the RDL (using SOP (Solder on Pad), Cu-pillar (copper pillar), or solder bump technologies 250)”); direct bonding is not shown. Furthermore, claim 11 is drawn to Fig. 4A given the requirement of an RDL; claim 11 is not drawn to Fig. 4B since said embodiment lacks an RDL.
Claim 25: “contacts of the second die are directly coupled to conductive structures at the second surface of the redistribution layer”.
Per Fig. 4A, element 250 is disclosed as “soldering of the components on to the RDL (using SOP (Solder on Pad), Cu-pillar (copper pillar), or solder bump technologies 250)”; direct coupling of contacts is not shown. Furthermore, base claim 1 is drawn to Fig. 4A given the requirement of an RDL; base claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
In addition, where are the “conductive structures at the second surface of the redistribution layer” shown? Base claim 1 already requires the redistribution layer comprising “at least one metallization layer”, hence both of these elements must be shown; both elements do not appear to be shown.
Claim 26: “the dielectric layer comprises a second dielectric material, and the second dielectric material is not between the second die and the second surface of the redistribution layer”
Per Fig. 5A, the dielectric layer/material 225 is between the second die 245 and the second surface of the redistribution layer. Furthermore, base claim 1 is drawn to Fig. 5A given the requirement of an RDL; base claim 1 is not drawn to Fig. 5B since said embodiment lacks an RDL.
Claim 27: “a surface of the second die is directly bonded to the second surface of the redistribution layer without intermediate connective structures”.
Per on Fig. 4A, the die 245 is not directly bonded to the RDL as there are intermediate structures (such as 250). Furthermore, base claim 1 is drawn to Fig. 4A given the requirement of an RDL; base claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-8, 11-18, 21-22 and 25-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 11, “wherein the second die is directly bonded to the second surface of the redistribution layer” (claim 1) and “directly bonding a second die to the second surface of the redistribution layer” (claim 11) are new matter.
Per Fig. 4A, the second die 245 is bonded to the RDL via element 250 (“soldering of the components on to the RDL (using SOP (Solder on Pad), Cu-pillar (copper pillar), or solder bump technologies 250)”); direct bonding is not shown or disclosed. Furthermore, claim 1 is drawn to Fig. 4A given the requirement of an RDL; claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
None of the dependent claims addresses these deficiencies.
Regarding claim 25: “contacts of the second die are directly coupled to conductive structures at the second surface of the redistribution layer” is new matter.
Per Fig. 4A, element 250 is disclosed as “soldering of the components on to the RDL (using SOP (Solder on Pad), Cu-pillar (copper pillar), or solder bump technologies 250)”; direct coupling of contacts is not shown or disclosed. Furthermore, base claim 1 is drawn to Fig. 4A given the requirement of an RDL; base claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
In addition, where are the “conductive structures at the second surface of the redistribution layer” disclosed? Base claim 1 already requires the redistribution layer comprising “at least one metallization layer”, hence both of these elements must be disclosed.
Regarding claim 26, “the dielectric layer comprises a second dielectric material, and the second dielectric material is not between the second die and the second surface of the redistribution layer” is new matter.
Per Fig. 5A, the dielectric layer/material 225 is between the second die 245 and the second surface of the redistribution layer. Furthermore, base claim 1 is drawn to Fig. 5A given the requirement of an RDL; base claim 1 is not drawn to Fig. 5B since said embodiment lacks an RDL.
Regarding claim 27, “a surface of the second die is directly bonded to the second surface of the redistribution layer without intermediate connective structures” is new matter.
Per on Fig. 4A, the die 245 is not directly bonded to the RDL as there are intermediate structures (such as 250). Furthermore, base claim 1 is drawn to Fig. 4A given the requirement of an RDL; base claim 1 is not drawn to Fig. 4B since said embodiment lacks an RDL.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 26, “a second dielectric material” is unclear as base claim 21 recites the same “a second dielectric material”. It is unclear if they refer to the same/different layers; treated as either.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, 11-14, 16-18, 21-22 and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (of record, US 20140103488 A1) in view of Zudock et al. (of record, US 8093711 B2).
Regarding claim 1, Chen discloses a device (Fig. 10), comprising:
a first die (25) having an uppermost surface, a bottommost surface, and a first side surface and a second side surface (left vs right) between the uppermost surface and the bottommost surface, the second side surface opposite the first side surface,
a molding (40) laterally adjacent to the first side surface and the second side surface of the first die, the molding having a (total) lateral width (Fig. 10);
a through mold via (28) in the molding extending vertically through a full height of the molding, and the through mold via laterally spaced apart from the first side surface of the first die (Fig. 10);
a redistribution layer (52/54) on the molding, the redistribution layer having a first surface (bottommost) and a second surface (topmost) opposite the first surface (Fig. 10), wherein the first surface (bottommost) is on and in direct physical contact with the uppermost surface of the first die (Fig. 10), the redistribution layer extends (at least) across a full width of the first die (Fig. 10), the redistribution layer (52/54) comprises a layer of a dielectric material (52) and at least one metallization layer (54, [0012]) formed therein, and the redistribution layer is coupled to the through mold via (28)
a dielectric layer (64) over the redistribution layer (52/54), the dielectric layer having a (total) lateral width the same as the (total) lateral width of the molding (40, Fig. 10);
a second die (58/62 per MPEP 2111 and not precluded by the claim) in the dielectric layer and coupled to the redistribution layer (52/54), wherein the second die (58/62) is directly bonded (at 62 Fig. 10) to the second surface (topmost) of the redistribution layer (Fig. 10), and the second die is electrically connected (per 54 and electrically connected at least at a package 66 level) to the through mold via (28) and to the first die (25); and
a plurality of solder balls (46) beneath the first die (25) and the molding (40), the plurality of solder balls on an opposite side of the first die from the redistribution layer (Fig. 10)
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Chen fails to disclose the first die having a through silicon via therein and the redistribution layer coupled to the through silicon via in the first die.
Zudock discloses the first die (42) having a through silicon via (44a/44b) therein and the redistribution layer (56a/48a/48b) coupled to the through silicon via in the first die (Fig. 2).
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It would have been obvious to one of ordinary skill in the art, before the effectively filling date, to provide the TSV arrangement of Zudock in Chen and arrive at the claimed invention so as to provide “provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption” (Zudock, 4:1-10).
Regarding claim 2, Chen/Zudock discloses the device of claim 1, wherein the molding (40) is in contact with the first side surface and the second side surface (left vs right) of the first die (25, Fig. 10).
Regarding claim 3, Chen/Zudock discloses the device of claim 1, further comprising: a second through mold via (another 28) in the molding and laterally spaced apart from the second (and first) side surface of the first die (Fig. 10).
Regarding claim 6, Chen/Zudock discloses the device of claim 1, wherein the molding (40) has an uppermost surface co-planar with the uppermost surface of the first die (25, Fig. 10).
Regarding claim 7, Chen/Zudock discloses the device of claim 1, wherein one or more of the plurality of solder balls (46) is vertically beneath the first die (25, Fig. 10).
Regarding claim 8, Chen/Zudock discloses the device of claim 1, wherein one or more of the plurality of solder balls (46) is vertically beneath the through mold via (as outermost 28, Fig. 10).
Regarding claim 21, Chen/Zudock discloses the device of claim 1, wherein the dielectric layer (64) comprises a second dielectric material in physical contact with the second die (58/62), the second dielectric material having the lateral width of the molding (Fig. 10).
Regarding claim 22, Chen/Zudock discloses the device of claim 1, wherein the through mold via (28) has a first end (bottom) at a first side (bottom) of the molding (40) and a second end (top) at a second side (top) of the molding (Fig. 10).
Regarding claim 25, Chen/Zudock discloses the device of claim 1, wherein contacts (MPEP 2111, 62) of the second die (58/62) are directly coupled to conductive structures (54) at the second surface (topmost) of the redistribution layer (52/54, Fig. 10).
Regarding claim 26, Chen/Zudock discloses the device of claim 21, wherein the dielectric layer (64) comprises a second dielectric material, and the second dielectric material is not between (at the place of direct physical contact between 62 and 54) the second die (58/62) and the second surface (topmost) of the redistribution layer (52/54, Fig. 10).
Regarding claim 27, Chen/Zudock discloses the device of claim 1, wherein a surface (at 62) of the second die (58/62) is directly bonded to the second surface (topmost) of the redistribution layer without intermediate connective structures (no intermediate elements between 62 and 54 at the place of direct physical contact between 62 and 54, Fig. 10).
Regarding claim 11, Chen discloses a method of fabricating a device, the method comprising:
providing a first die (25) having an uppermost surface, a bottommost surface, and a first side surface and a second side surface (left vs right) between the uppermost surface and the bottommost surface, the second side surface opposite the first side surface (Fig. 10)
forming a molding (40) laterally adjacent to the first side surface and the second side surface of the first die, the molding having a (total) lateral width (Fig. 10);
forming a through mold via (28) in the molding extending vertically through a full height of the molding (Fig. 10), and the through mold via laterally spaced apart from the first side surface of the first die (Fig. 10);
forming a redistribution layer (52/54) on the molding, the redistribution layer having a first surface (bottommost) and a second surface (topmost) opposite the first surface, the first surface (bottommost) of the redistribution layer on and in direct physical contact with the uppermost surface of the first die (25), the redistribution layer extending (at least) across a full width of the first die, the redistribution layer comprising a layer of a dielectric material (52) and at least one metallization layer (54) formed therein, and the redistribution layer (52/54) coupled to the through mold via
directly bonding a second die (58/62 per MPEP 2111 and not precluded by the claim) to the second surface (topmost) of the redistribution layer (52/54), the second die electrically connected (per 54 and electrically connected at least at a package 66 level) to the through mold via and to the first die (Fig. 10);
forming a dielectric layer (64) over the redistribution layer and the second die, wherein the second die is in the dielectric layer, the dielectric layer having a (total) lateral width the same as the (total) lateral width of the molding (Fig. 10); and
forming a plurality of solder balls (46) beneath the first die and the molding, the plurality of solder balls on an opposite side of the first die from the redistribution layer (Fig. 10).
Chen fails to disclose the first die having a through silicon via therein and the redistribution layer coupled to the through silicon via in the first die.
Zudock discloses the first die (42) having a through silicon via (44a/44b) therein and the redistribution layer (56a/48a/48b) coupled to the through silicon via in the first die (Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effectively filling date, to provide the TSV arrangement of Zudock in Chen and arrive at the claimed invention so as to provide “provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption” (Zudock, 4:1-10).
Regarding claim 12, Chen/Zudock discloses the method of claim 11, wherein the molding (40) is in contact with the first side surface and the second side surface (left/right) of the first die (25, Fig. 10).
Regarding claims 13 and 14, Chen/Zudock discloses (claim 13) the method of claim 11, further comprising: forming a second through mold via (another 28) in the molding and laterally spaced apart from the second (and first) side surface of the first die (Fig. 10), and, (claim 14) wherein the second die (58/62) is electrically connected (per 54 and electrically connected at least at a package 66 level) to the second through mold via (Fig. 10).
Regarding claim 16, Chen/Zudock discloses the method of claim 11, wherein the molding (40) has an uppermost surface co-planar with the uppermost surface of the first die (25, Fig. 10).
Regarding claim 17, Chen/Zudock discloses the method of claim 11, wherein one or more of the plurality of solder balls (46) is vertically beneath the first die (25, Fig. 10).
Regarding claim 18, Chen/Zudock discloses the method of claim 11, wherein one or more of the plurality of solder balls (46) is vertically beneath the through mold via (as outermost 28, Fig. 10).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (of record, US 20140103488 A1) in view of Zudock et al. (of record, US 8093711 B2) as applied to claims 1 and 11 above, and further in view of Chen et al. (“Chen2”of record, US 20170125379 A1).
Regarding claims 5 and 15, Chen/Zudock fail to disclose wherein the second die has an uppermost surface co-planar with an uppermost surface of the dielectric layer.
Chen2 discloses wherein the second die (200) has an uppermost surface co-planar with an uppermost surface of the dielectric layer (700, per 100, Figs. 11 and 13).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Chen2 in Chen/Zudock and arrive at the claimed invention so as to enable providing a heatsink over the second die and thereby enable heat dissipation away from the package.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (of record, US 20140103488 A1) in view of Zudock et al. (of record, US 8093711 B2) as applied to claims 1 and 11 above, and further in view of Hofstee et al. (of record, US 6507115 B2).
Regarding claims 5 and 15, Chen/Zudock fail to disclose wherein the second die has an uppermost surface co-planar with an uppermost surface of the dielectric layer.
Hofstee discloses wherein the second die (204) has an uppermost surface co-planar with an uppermost surface of the dielectric layer (202. Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Hofstee in Chen/Zudock and arrive at the claimed invention so as to enable the possibility of adding a heatsink directly the second die which would “improve the ability of module 200 to dissipate heat” as disclosed by Hofstee.
Response to Arguments
Applicant's arguments filed 4.29.2026 have been fully considered but they are not persuasive. The applicant alleges:
“As amended herein, claim 1 specifies that the redistribution layer has a first surface and a second surface opposite the first surface, and further requires that "the second die is directly bonded to the second surface of the redistribution layer." This is not shown in the cited references. Chen discloses a package-on-package arrangement in which a second package 66, which includes the alleged second die 58, is bonded to the bottom package 48, which includes dielectric layers 52 and RDLs 54. See Paragraph [0018]. Package component 58 is not bonded directly to the RDLs 54, but instead, is coupled to the RDLs 54 by connectors 62, which are illustrated as solder balls. Zudock is relied upon for showing TSVs and also does not disclose the amended limitations.”.
This is not persuasive as, in the current rejection, the second die is interpreted as 58/62 per MPEP 2111 wherein said interpretation is not precluded by the claim.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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