DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1.20.2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 11-14, 16-18 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20140103488 A1) in view of Zudock et al. (US 8093711 B2).
Regarding claim 1, Chen discloses a device (Fig. 10), comprising:
a first die (25) having an uppermost surface, a bottommost surface, and a first side surface and a second side surface (left vs right) between the uppermost surface and the bottommost surface, the second side surface opposite the first side surface,
a molding (40) laterally adjacent to the first side surface and the second side surface of the first die, the molding having a (total) lateral width (Fig. 10);
a through mold via (28) in the molding extending vertically through a full height of the molding, and the through mold via laterally spaced apart from the first side surface of the first die (Fig. 10);
a redistribution layer (52/54) on the molding, the redistribution layer on and in direct physical contact with the uppermost surface of the first die (Fig. 10), the redistribution layer extending (at least) across a full width of the first die (Fig. 10), the redistribution layer (52/54) comprising a layer of a dielectric material (52) and at least one metallization layer (54, [0012]) formed therein, and the redistribution layer coupled to the through mold via (28)
a dielectric layer (64) over the redistribution layer (52/54), the dielectric layer having a (total) lateral width the same as the (total) lateral width of the molding (40, Fig. 10);
a second die (58) in the dielectric layer and coupled to the redistribution layer (52/54), the second die electrically connected (per 54 and electrically connected at least at a package 66 level) to the through mold via (28) and to the first die (25); and
a plurality of solder balls (46) beneath the first die (25) and the molding (40), the plurality of solder balls on an opposite side of the first die from the redistribution layer (Fig. 10)
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Chen fails to disclose the first die having a through silicon via therein and the redistribution layer coupled to the through silicon via in the first die.
Zudock discloses the first die (42) having a through silicon via (44a/44b) therein and the redistribution layer (56a/48a/48b) coupled to the through silicon via in the first die (Fig. 2).
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It would have been obvious to one of ordinary skill in the art, before the effectively filling date, to provide the TSV arrangement of Zudock in Chen and arrive at the claimed invention so as to provide “provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption” (Zudock, 4:1-10).
Regarding claim 2, Chen/Zudock discloses the device of claim 1, wherein the molding (40) is in contact with the first side surface and the second side surface (left vs right) of the first die (25, Fig. 10).
Regarding claims 3 and 4, Chen/Zudock discloses (claim 3) the device of claim 1, further comprising: a second through mold via (another 28) in the molding and laterally spaced apart from the second (and first) side surface of the first die (Fig. 10), and, (claim 4) ) the device of claim 3, wherein the second die (58) is electrically connected (per 54 and electrically connected at least at a package 66 level) to the second through mold via (Fig. 10).
Regarding claim 6, Chen/Zudock discloses the device of claim 1, wherein the molding (40) has an uppermost surface co-planar with the uppermost surface of the first die (25, Fig. 10).
Regarding claim 7, Chen/Zudock discloses the device of claim 1, wherein one or more of the plurality of solder balls (46) is vertically beneath the first die (25, Fig. 10).
Regarding claim 8, Chen/Zudock discloses the device of claim 1, wherein one or more of the plurality of solder balls (46) is vertically beneath the through mold via (as outermost 28, Fig. 10).
Regarding claim 21, Chen/Zudock discloses the device of claim 1, wherein the dielectric layer (64) comprises a dielectric material in physical contact with the second die (58), the dielectric material having the lateral width of the molding (Fig. 10).
Regarding claim 22, Chen/Zudock discloses the device of claim 1, wherein the through mold via (28) has a first end (bottom) at a first side (bottom) of the molding (40) and a second end (top) at a second side (top) of the molding (Fig. 10).
Regarding claim 23, Chen/Zudock discloses the device of claim 1, wherein the redistribution layer (52/54) further extends across a full width of the molding (40, Fig. 10).
Regarding claim 24, Chen/Zudock discloses the device of claim 1, , wherein the dielectric material (52, [0016]) of the redistribution layer (52/54) is different from the molding (40, [0011]).
Regarding claim 11, Chen discloses a method of fabricating a device, the method comprising:
providing a first die (25) having an uppermost surface, a bottommost surface, and a first side surface and a second side surface (left vs right) between the uppermost surface and the bottommost surface, the second side surface opposite the first side surface (Fig. 10)
forming a molding (40) laterally adjacent to the first side surface and the second side surface of the first die, the molding having a (total) lateral width (Fig. 10);
forming a through mold via (28) in the molding extending vertically through a full height of the molding (Fig. 10), and the through mold via laterally spaced apart from the first side surface of the first die (Fig. 10);
forming a redistribution layer (52/54) on the molding, the redistribution layer on and in direct physical contact with the uppermost surface of the first die (25), the redistribution layer extending (at least) across a full width of the first die, the redistribution layer comprising a layer of a dielectric material (52) and at least one metallization layer (54) formed therein, and the redistribution layer (52/54) coupled to the through mold via
coupling a second die (58) to the redistribution layer (52/54), the second die electrically connected (per 54 and electrically connected at least at a package 66 level) to the through mold via and to the first die (Fig. 10);
forming a dielectric layer (64) over the redistribution layer and the second die, wherein the second die is in the dielectric layer, the dielectric layer having a (total) lateral width the same as the (total) lateral width of the molding (Fig. 10); and
forming a plurality of solder balls (46) beneath the first die and the molding, the plurality of solder balls on an opposite side of the first die from the redistribution layer (Fig. 10).
Chen fails to disclose the first die having a through silicon via therein and the redistribution layer coupled to the through silicon via in the first die.
Zudock discloses the first die (42) having a through silicon via (44a/44b) therein and the redistribution layer (56a/48a/48b) coupled to the through silicon via in the first die (Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effectively filling date, to provide the TSV arrangement of Zudock in Chen and arrive at the claimed invention so as to provide “provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption” (Zudock, 4:1-10).
Regarding claim 12, Chen/Zudock discloses the method of claim 11, wherein the molding (40) is in contact with the first side surface and the second side surface (left/right) of the first die (25, Fig. 10).
Regarding claims 13 and 14, Chen/Zudock discloses (claim 13) the method of claim 11, further comprising: forming a second through mold via (another 28) in the molding and laterally spaced apart from the second (and first) side surface of the first die (Fig. 10), and, (claim 14) wherein the second die (58) is electrically connected (per 54 and electrically connected at least at a package 66 level) to the second through mold via (Fig. 10).
Regarding claim 16, Chen/Zudock discloses the method of claim 11, wherein the molding (40) has an uppermost surface co-planar with the uppermost surface of the first die (25, Fig. 10).
Regarding claim 17, Chen/Zudock discloses the method of claim 11, wherein one or more of the plurality of solder balls (46) is vertically beneath the first die (25, Fig. 10).
Regarding claim 18, Chen/Zudock discloses the method of claim 11, wherein one or more of the plurality of solder balls (46) is vertically beneath the through mold via (as outermost 28, Fig. 10).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20140103488 A1) in view of Zudock et al. (US 8093711 B2) as applied to claims 1 and 11 above, and further in view of Chen et al. (“Chen2”of record, US 20170125379 A1).
Regarding claims 5 and 15, Chen/Zudock fail to disclose wherein the second die has an uppermost surface co-planar with an uppermost surface of the dielectric layer.
Chen2 discloses wherein the second die (200) has an uppermost surface co-planar with an uppermost surface of the dielectric layer (700, per 100, Figs. 11 and 13).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Chen2 in Chen/Zudock and arrive at the claimed invention so as to enable providing a heatsink over the second die and thereby enable heat dissipation away from the package.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20140103488 A1) in view of Zudock et al. (US 8093711 B2) as applied to claims 1 and 11 above, and further in view of Hofstee et al. (of record, US 6507115 B2).
Regarding claims 5 and 15, Chen/Zudock fail to disclose wherein the second die has an uppermost surface co-planar with an uppermost surface of the dielectric layer.
Hofstee discloses wherein the second die (204) has an uppermost surface co-planar with an uppermost surface of the dielectric layer (202. Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Hofstee in Chen/Zudock and arrive at the claimed invention so as to enable the possibility of adding a heatsink directly the second die which would “improve the ability of module 200 to dissipate heat” as disclosed by Hofstee.
Response to Arguments
Applicant’s arguments, filed 1.20.2026, with respect to Fig. 9, [0041], [0060] and [0083-0085] provide support for claims 3-4 and 13-14 have been fully considered and are persuasive. The drawing objections and 35 USC 112 rejections of claims 3-4 and 13-14 have been withdrawn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/ Primary Examiner, Art Unit 2818