DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1–3, 5–6, 8–9, 11–12, 14–15, 17, and 19–20, drawn to FIGS. 1–10, in the reply filed August 3, 2026 is acknowledged1. Those claims are examined. Claims 4, 7, 10, 13, 16, and 18, drawn to an inter-gate electrode wiring, are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being directed to a non-elected species.
The withdrawn claims will be eligible for rejoinder if the elected claims are found allowable and the withdrawn claims require all the limitations of an allowable claim.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)–(d) based on Japanese Application No. 2023-151654, filed September 19, 2023.
Receipt is acknowledged of aforementioned certified copies of papers required by 37 CFR 1.55 electronically retrieved in April 3, 2026.
Information Disclosure Statement
The information disclosure statements filed March 11, 2024 and August 3, 2026, both filed before first Office action, have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Device with Gate Electrodes on Crossed Field Plates.
Drawings
The drawings filed March 11, 2024 are accepted.
Claim Interpretation
The claims are given their broadest reasonable interpretation consistent with the specification. MPEP § 2111.
A field plate electrode reads on an electrode that is buried in the drift region through an insulating film and held at the source potential. Kawamura calls that electrode a trench source electrode. The name does not take it outside the claim.
“Provided on the insulating films” is the portion of the gate that overlies the insulating film in which the field plate electrode is embedded. FIG. 3C of Kawamura is that arrangement. “On” is not limited to direct contact with nothing else between the gate and that film.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites “the insulating film is a thermal oxide film.” Claim 1 recites “insulating films” and “a gate insulating film.” There is no antecedent basis for “the insulating film.” It is not clear which film is the thermal oxide. Claim 9 depends from claim 8 and is indefinite for the same reason.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura et al., U.S. Patent No. 8,968,017 B2 (issued March 3, 2015; cited on the IDS) in view of Omura et al., U.S. Patent No. 6,750,508 B2 (issued June 15, 2004; cited on the IDS).
Regarding independent claim 1, Kawamura teaches a semiconductor device comprising:
a first electrode (drain electrode 12 on the back of n+ substrate 11; FIG. 3A);
a first semiconductor region of a first conductivity type provided on the first electrode (n− drift layer 2 on substrate 11, which is on drain electrode 12; the drift layer is n-type; FIG. 3A);
a second semiconductor region of a second conductivity type provided on the first semiconductor region (p-type base region 13 between source region 5 and drift layer 2; FIGS. 3A and 3D);
a third semiconductor region of a first conductivity type provided on the second semiconductor region (n+ source region 5 on base region 13; FIG. 3A);
a plurality of field plate electrodes provided in the first semiconductor region via insulating films and extending along a first direction (trench source electrodes 6 in drift layer 2 through insulating films 7, extending in the Y direction; FIG. 3D); and
a plurality of gate electrodes extending along a second direction different from the first direction, the plurality of gate electrodes including first conductive portions provided in the second semiconductor region via a gate insulating film, and second conductive portions coupled to the first conductive portions and provided on the insulating films (trench gate electrodes 3 extend in the X direction, crossing the Y-direction field plates; the portions of gate electrode 3 that face base region 13 are the first conductive portions, through gate insulating film 4, FIG. 3A; the portions of the same gate electrode 3 that overlie insulating film 7, where the gate crosses trench 10, are the second conductive portions, FIG. 3C).
The X direction and the Y direction cross. Kawamura states that the extending direction of trench gate electrodes 3 is orthogonal to the extending direction of trench source electrodes 6.
Kawamura does not teach a second electrode in contact with the second semiconductor region and the third semiconductor region at contact portions. Source electrode 8 is electrically connected to source region 5 and to trench source electrode 6 (¶ [0053]; FIGS. 3A and 3D). P-type base region 13 is between n+ source region 5 and n− drift layer 2, and source electrode 8 does not contact base region 13 (¶ [0056]; FIGS. 3A and 3D).
Base region 13 is left floating between the n+ source and the n− drift. The n+ source, the p-type base, and the n− drift are a parasitic bipolar transistor, and Kawamura does not hold the base at the source potential.
Omura provides the contact that holds the base at the source potential. In FIG. 2, source electrodes 21 are formed on p-type well layers 13 and are connected to n-type source layers 14 and to well layers 13. The source electrode reaches the p-type well, not only the n-type source, and the well is held at the source potential.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form contact portions of Kawamura’s source electrode 8 through source region 5 and into base region 13, as Omura forms source electrode 21 on well layer 13, so that electrode 8 contacts the p-type base and the n-type source and the base is held at the source potential.
Regarding dependent claim 2, Kawamura teaches wherein between the plurality of gate electrodes and the plurality of field plate electrodes, a semiconductor region is not interposed and only the insulating films are provided (FIG. 3C: where gate electrode 3 crosses trench source electrode 6, gate insulating film 4 and insulating film 7 are between them, and drift layer 2 is not).
Regarding dependent claim 3, Kawamura teaches wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2: each gate electrode 3 is a continuous stripe in the X direction and is taken out at its end to gate extraction interconnection 14a at the periphery; no wiring is provided between the adjacent portions of the gate that overlie the field-plate insulating films).
Regarding dependent claim 5, Kawamura teaches wherein the second conductive portions are provided so as to straddle the insulating films in which the field plate electrode is embedded (FIG. 3C: gate electrode 3 extends in the X direction across insulating film 7 and continues on both sides of trench 10).
Regarding dependent claim 6, Kawamura teaches the device of claim 5, wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2, as mapped for claim 3).
Regarding dependent claim 8, to the extent the claim is understood as requiring the insulating film in which the field plate electrode is embedded to be a thermal oxide, Kawamura teaches the insulating film is a thermal oxide film (insulating film 7 is formed by thermal oxidation). The same obviousness combination used for claim 1 applies.
Regarding dependent claim 9, Kawamura teaches the device of claim 8, wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2, as mapped for claim 3).
Regarding dependent claim 11, Kawamura teaches wherein the first direction and the second direction are directions orthogonal to each other (the Y direction of trench source electrodes 6 is orthogonal to the X direction of trench gate electrodes 3).
Regarding dependent claim 12, Kawamura teaches the device of claim 11, wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2, as mapped for claim 3).
Regarding dependent claim 14, Kawamura teaches wherein an upper end of the field plate electrode is located above a lower end of the second semiconductor region (FIG. 3D: trench source electrode 6 extends up through base region 13 into source region 5, so the upper end of electrode 6 is above the lower end of base region 13).
Regarding dependent claim 15, Kawamura teaches the device of claim 14, wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2, as mapped for claim 3).
Regarding dependent claim 17, Kawamura teaches wherein a wiring that electrically couples the plurality of gate electrodes is not provided between the adjacent second conductive portions (FIG. 2, as mapped for claim 3).
Regarding dependent claim 19, Kawamura teaches wherein each of the plurality of gate electrodes alternately has the first conductive portions and the second conductive portions (each gate electrode 3 runs in the X direction across successive trenches 10; between those trenches the gate is in base region 13 through gate insulating film 4, FIG. 3A, and at each trench 10 the gate is on insulating film 7, FIG. 3C).
Regarding dependent claim 20, Kawamura teaches wherein the first conductivity type is an n-type, and the second conductivity type is a p-type (drift layer 2 and source region 5 are n-type; base region 13 is p-type).
Conclusion
Claims 1–3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 19, and 20 are rejected under 35 U.S.C. 103. Claims 8 and 9 are also rejected under 35 U.S.C. 112(b). Claims 4, 7, 10, 13, 16, and 18 are withdrawn.
A shortened statutory period for reply to this non-final action is set to expire THREE MONTHS from the mailing date of this communication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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28 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Requirement for Restriction/Election dated June 3, 2026.
