Prosecution Insights
Last updated: October 27, 2026

John P Dulka, USPTO Patent Examiner

Listed by the USPTO as DULKA, JOHN P

Tech Center 2800 • Art Units: 2800 2817 2895

This examiner grants 84% of resolved cases

Analysis

John P. Dulka, in Tech Center 2800 and Art Unit 2800, has 864 resolved cases. The allowance rate is 83.8 percent. The median days to allowance is 926.

The interview lift is 12.3 percent. Taiwan Semiconductor Manufacturing Company, Ltd., Robert Bosch GmbH, and Samsung Electronics Co., Ltd. are the top companies. These companies represent the primary corporate interests in the examiner's docket.

NORTON ROSE FULBRIGHT US LLP, VOLPE KOENIG, and Bridgeway IP Law Group, PLLC are the top firms. The 83.8 percent allowance rate is high. Practitioners should use the 12.3 percent interview lift to navigate the 926-day median timeline.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

83.8%
Allow Rate
+15.8% vs TC avg
897
Total Applications
+12.3%
Interview Lift
926
Avg Prosecution Days
Based on 864 resolved cases, 2023–2026

Rejection Statute Breakdown

0.7%
§101 Eligibility
29.1%
§102 Novelty
40.5%
§103 Obviousness
22.9%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18308376 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18910885 METHOD FOR MANUFACTURING A VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE AND CORRESPONDING VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE Non-Final OA Robert Bosch GmbH
18716559 METHOD FOR PRODUCING A POWER FINFET, AND POWER FINFET Non-Final OA Robert Bosch GmbH
18602028 DISPLAY DEVICE AND METHOD FOR FABRICATION THEREOF Non-Final OA Samsung Display Co., LTD.
18601851 SEMICONDUCTOR DEVICE Non-Final OA Toshiba Electronic Devices & Storage Corporation
18911277 CHIP AND PREPARATION METHOD THEREOF, AND ELECTRONIC DEVICE Non-Final OA HUAWEI TECHNOLOGIES CO., LTD.
18729091 SEMICONDUCTOR MODULE Non-Final OA KYOCERA Corporation
18545188 SEMICONDUCTOR DEVICE WITH STACKED DEVICE TYPES Final Rejection INTERNATIONAL BUSINESS MACHINES CORPORATION
18772644 POWER CONVERSION CIRCUIT, POWER MODULE, CONVERTER, AND INVERTER Non-Final OA ROHM CO., LTD.
18602163 THERMAL CONDUCTIVE BONDING STRUCTURE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18745760 Etch Profile Control Of Polysilicon Structures Of Semiconductor Devices Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18785009 METAL-INSULATOR-METAL CAPACITORS WITH THICK INTERMEDIATE ELECTRODE LAYERS AND METHODS OF FORMING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Company Limited
18767026 STRETCHABLE DEVICE Non-Final OA Magnolia White Corporation
18790300 HEATER, TEMPERATURE CONTROL SYSTEM, AND PROCESSING APPARATUS Non-Final OA Kokusai Electric Corporation
18771588 HIGH-VOLTAGE APPLICATION OF LOW-VOLTAGE-TOLERANT MULTI-LAYER CAPACITORS Non-Final OA Advanced Micro Devices, Inc.

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Frequently Asked Questions

What is examiner John P Dulka's allowance rate?

83.8% of resolved applications examined by John P Dulka were allowed (864 resolved cases), compared with 69.7% across Art Unit 2800 over the last five years.

Does an interview help with examiner John P Dulka?

This examiner's interview lift is +12.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner John P Dulka take to allow a patent?

Applications allowed by John P Dulka took 926 days on average from filing to allowance.

Which art unit does examiner John P Dulka work in?

John P Dulka examines applications in Art Unit 2800 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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