DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I drawn to Figs. 2-4 and claims 1-4 and 9-11 in the reply filed on 7/20/2026 is acknowledged.
Claims 5-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on7/20/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hoshino et al. (US 20100295602 A1), hereinafter referred to as “Hoshino602”.
Regarding claim 1: Hoshino602 teaches a semiconductor device comprising: a substrate (“As shown in FIGS. 2 and 3, the substrate 2 is, for example, a dielectric substrate, and has signal patterns, wiring patterns and lands that are formed on a surface of the substrate 2.”, para. [0033]); a first transistor and a second transistor (“For example, the semiconductor switch 41 (a first semiconductor switch) is a surface mount N channel MOSFET having a drain (D), a source (S) and a gate (G), and is used to make or break the connection between the signal patterns 201 and 203. Similarly, the semiconductor switch 42 (a second semiconductor switch) is a surface mount N channel MOSFET having a drain (D), a source (S) and a gate (G), and is used to make or break the connection between the signal patterns 202 and 203.”, para. [0036]) provided above a first surface of the substrate (All elements of the device are illustrated as being on the top surface of substrate 2 in Fig. 3) and having their sources commonly coupled to each other (“the sources of the semiconductor switches 41 and 42 are mutually connected and thereby the anodes of both body diodes are mutually connected.”, para. [0036]”); a light emitting element provided above the first surface of the substrate and having an anode electrode and a cathode electrode (“In the example of FIG. 3, the light emitting element 70 is a surface mount device, and the anode and cathode of the light emitting element 70 are located on the bottom and top surfaces of the device, respectively.”, para. [0042]); a light receiving element provided above the first surface of the substrate and turning on or off the first transistor and the second transistor depending on a light emission state of the light emitting element (“For example, the control IC 60 includes a light receiving element (e.g., a photodiode array) for obtaining the input signal by receiving the light from the light emitting element 70, and is configured to control the semiconductor switches 41 and 42 in response to the input signal.”, para. [0043]); a first filter element provided above the first surface of the substrate (“The composite filter 73 is a first low-pass filter configured to attenuate frequencies higher than a predetermined cut off frequency”, para. [0040]) and coupled to the anode electrode of the light emitting element; and a second filter element (“The composite filter 74 is a second low-pass filter configured to attenuate higher frequencies than a predetermined cut-off frequency”, para. [0041]) provided above the first surface of the substrate and coupled to the cathode electrode of the light emitting element (See Fig. 3, “the anode and cathode of the light emitting element 70 are located on the bottom and top surfaces of the device, respectively. The light emitting element 70 is mounted on a land 224 formed at a second end of the wiring pattern 223 by die bonding, and thereby the anode of the light emitting element 70 is directly connected to the land 224. The cathode of the light emitting element 70 is connected to a second end of the wiring pattern 233 through, for example, a bonding wire 700. The wiring patterns 223 and 233 (especially the land 224) are located in the proximity of the control IC 60.”, para. [0042], filters 73 and 74 are coupled to the anode and cathode through wiring patterns 223 and 233 along with bond wire 700 in Fig. 3).
Regarding claim 2: Hoshino602 teaches the device of claim 1, further comprising a first wiring (See Fig. 3 wiring pattern 223) that electrically couples the first filter element and the anode electrode of the light emitting element to each other (“The light emitting element 70 is mounted on a land 224 formed at a second end of the wiring pattern 223 by die bonding, and thereby the anode of the light emitting element 70 is directly connected to the land 224.”, para. [0042]), and a second wiring (Fig. 3 wiring pattern 233) that electrically couples the second filter element and the cathode electrode of the light emitting element to each other (“The cathode of the light emitting element 70 is connected to a second end of the wiring pattern 233 through, for example, a bonding wire 700. The wiring patterns 223 and 233 (especially the land 224) are located in the proximity of the control IC 60.”, para. [0042], wherein the first wiring and the second wiring are arranged substantially parallel to each other as viewed from above (See Fig. 3, elements 223 and 233 are depicted as being offset and substantially parallel to each other from the top-view).
Regarding claim 3: Hoshino602 teaches the device of claim 2, wherein the first filter element includes a first filter electrode and a second filter electrode (“First and second ends of the LPF 731 are connected to a second end (a land) of the wiring pattern 221 and a first end (a land) of a wiring pattern 222, respectively.”, para. [0064] and the second filter element includes a third filter electrode and a fourth filter electrode. (“First and second ends of the LPF 732 are connected to a second end (a land) of the wiring pattern 222 and a first end (a land) of a wiring pattern 223, respectively.”, para. [0064])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (US 20100295602 A1), hereinafter referred to as “Hoshino602”, in view of Chen (US 20110085311 A1) hereinafter referred to as “Chen311”.
Regarding claim 4: Hoshino602 teaches the device of claim 3. Hoshino602 does not explicitly teach that the first filter electrode and the second filter electrode oppose each other in a first direction perpendicular to the first surface, the third filter electrode and the fourth filter electrode oppose each other in the first direction, the first filter electrode is provided on an upper surface of the first filter element, the second filter electrode is provided on a lower surface of the first filter element, the third filter electrode is provided on an upper surface of the second filter element, and the fourth filter electrode is provided on a lower surface of the second filter element.
Chen311 teaches a method for forming a vertically stacked passive component on a substrate (“A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.”, abstract). Chen also teaches that these passive elements may form a low-pass filter (“FIG. 9 shows example implementations of a low-pass filter using one or more vertically-structured passive components according to embodiments of the present invention.”, para. [0019])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Hoshino602 could be modified, by replacing the low-pass filter elements (Fig. 3 of Hoshino 602, elements 73 and 74) with the vertical low-pass filter configuration disclosed in Chen311, in order to arrive at the claimed invention. In this case, the first filter electrode and the second filter electrode oppose each other in a first direction perpendicular to the first surface (The contact electrodes are stacked vertically, while the top surface of the substrate is considered to extend horizontally), the third filter electrode and the fourth filter electrode oppose each other in the first direction (The third and fourth filter electrodes would have the same orientation as the first and second electrodes) the first filter electrode is provided on an upper surface of the first filter element, the second filter electrode is provided on a lower surface of the first filter element (See Fig. 9 of Chen311, Pin 3 pad contact and Out 3 Target contact are two electrodes that oppose each other vertically), the third filter electrode is provided on an upper surface of the second filter element, and the fourth filter electrode is provided on a lower surface of the second filter element (The third and fourth filter electrodes would have the same orientation as the first and second electrodes). Such a modification would be recognized by a person of ordinary skill in the art as having the advantage of reducing the area of a semiconductor package and could be performed with a reasonable expectation of success.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (US 20100295602 A1), hereinafter referred to as “Hoshino602”, in view of Morikita et al. (US 20110013349 A1) hereinafter referred to as Morikita349.
Regarding claim 9: Hosino602 teaches the device of claim 1. Hosino602 does not teach that the first filter element and the second filter element are integrally provided.
Morikita349 teaches an electronic component module with multiple passive components (“The surface mount component 3 is preferably a passive chip component, such as a chip capacitor, a chip inductor, or a chip resistor, for example.”, para. [0035]) that are integrally formed (“The electronic component module 21 illustrated in FIG. 9 includes a circuit substrate 22 including the surface mount components 2 and 3 mounted thereon, the resin layer 4 covering the surface mount components 2 and 3, and a conductor layer 24 which is provided on the surface of the resin layer 4 and defines an antenna. Conductive posts 23 are provided on the surface mount components 3, and the surface mount components 3 are connected to the conductor layer 24 through the conductive posts 23.”, para. [0060]).
Morikita349 also recognizes that forming electronic components integrally and surrounded by a shielding layer may protect high-frequency components from being influenced by their surroundings. (“To prevent such a high-frequency module arranged in a casing, a motherboard, or other component from being electromagnetically influenced by various surrounding electronic devices, or to prevent the high-frequency module from electromagnetically influencing the various electronic devices, a configuration may be used in which the surface mount components mounted on the circuit substrate are covered with a shielding layer having a ground potential.”, para. [0005]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Hosino609 could be modified so that the low-pass filter components were formed integrally and encapsulated with a shielding layer, guided by the teachings of Morikita349, to arrive at the claimed invention. A person of ordinary skill in the art would recognize the advantage of isolating the high frequency components from their surroundings and that such a modification could be made with a reasonable chance of success.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (US 20100295602 A1), hereinafter referred to as “Hoshino602”, in view of Fujihara (US 20200161494 A1) hereinafter referred to as “Fujihara494”.
Regarding claim 10: Hoshino602 teaches the device of claim 1. Hoshino602 does not teach the light emitting element and the light receiving element are sandwiched in a first direction parallel to the first surface between the first filter element and the second filter element and the first transistor and the second transistor.
Fujihara494 teaches a photocoupling device where the light emitting device is mounted on the light receiving device in the center of a surface mounted package (See at least Fig. 1A, “The photocoupler includes an input terminal 50, an output terminal 53, a first MOSFET 31, a second MOSFET 32, a semiconductor light receiving element 20, a semiconductor light emitting element 10, and a resin layer 90.”, para. [0017]). Fujihara recognizes that such a configuration can increase the density of the package components (“Applications such as machine tool control and semiconductor testers increasingly require speed-up of the photocoupler. For instance, they require high-frequency passing characteristics of 5 GHz or more. Furthermore, these applications need numerous photocouplers in order to configure a system. In these cases, a surface-mounted package having a small footprint and low profile is required for high-density mounting on a circuit substrate.”, para. [0004])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Hoshino602 could be modified, according to the teachings of Fujihara494, so that the light emitting device is stacked onto the light receiving device in the center of the substrate to arrive at the claimed invention. A person of ordinary skill in the art would recognize that such a configuration would have the advantage of improved circuit density and that such a modification could be made with a reasonable chance of success.
Regarding claim 11: Hoshino602 teaches the device of claim 3. Hoshino602 does not teach a first terminal, a second terminal, a third terminal, and a fourth terminal that are provided below the first surface, wherein the first terminal is coupled to the second filter electrode through a via penetrating the substrate, the second terminal is coupled to the fourth filter electrode through a via penetrating the substrate, the third terminal is coupled to a drain of the first transistor through a via penetrating the substrate, and the fourth terminal is coupled to a drain of the second transistor through a via penetrating the substrate.
Fujihara494 explicitly teaches at least two backside contacts (See Fig. 4B elements 157 and 158) which are connected to the transistors through the substrate (“On the die pads 161, 162, the first and second MOSFETs 131, 132, respectively, the semiconductor light receiving element 120, and the semiconductor light emitting element 110 are provided in this order. The insulating substrate 140 is provided with through holes. The through holes are buried with buried conductor layers 171, 172 for connecting the die pads 161, 162 and the back surface conductive layer of the output terminal 153, respectively. A conductive layer is provided on the side surface of the insulating substrate 140 on the output terminal 153 side in order to form a solder fillet. For instance, in FIG. 4B, the fourth conductive region 155 of the output terminal 153 is connected to a back side conductive region 157 through a via conductive region 156 provided on the sidewall of a notch part provided in a second surface 142 of the insulating substrate 140. Likewise, via conductive regions and back side conductive regions are provided also for the first conductive region 151, the second conductive region 152, and the third conductive region 154.”, para. [0043]) two more backside regions are mentioned (“back side conductive regions are provided also for the first conductive region 151, the second conductive region 152”, para. [0043]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed in Hosino602, guided by the teachings of Fujihara494, to have backside contacts connected to the filter elements and therefore arrive at the claimed invention. A person of ordinary skill in the art would recognize the advantage of mounting the semiconductor chip onto a chip substrate to increase device density and integration and that such a modification could be performed with a reasonable chance of success.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Hirano (US 20220256708 A1) teaches mounting passive devices, such as ferrite beads for low-pass filters on a substrate surface, which may also be connected to the anode and cathode of a light emitting device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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