DETAILED ACTION
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. US 2010/0118596 A1.
Regarding claims 1, 2, 4-9 and 14-18, Jeong discloses:
A system-on-chip, comprising:
a digital module (101 access transistor, 103 logic, 104 I/O circuit) and an embedded memory module (102 capacitor), wherein the digital module comprises at least one first metal-oxide-semiconductor (MOS) transistor (104) and at least one standard cell (103), and the embedded memory module comprises at least one embedded memory cell (102); and
wherein the standard cell comprises at least one second MOS transistor (103), and the embedded memory cell comprises at least one third MOS transistor (102), each of the first MOS transistor, the second MOS transistor, and the third MOS transistor comprises a gate (Fig. 4D in view of gate shown in Fig. 3I) and a gate oxide layer (49, 45, 43) underlying the gate, and the gate oxide layers of the second MOS transistor and the third MOS transistors are both thinner than the gate oxide layer of the first MOS transistor (para 0034; “The resulting structure shown in FIG. 4D has a thickness of approximately 15-28 A for gate oxide 41 of the access transistor, 30-40 A for the capacitor dielectric 43, 15-28 A for the logic gate dielectric 45; and for the I/O gate, a gate oxide 49 of approximately 50-70 A.”).
Although Jeong does not specifically disclose “the gate oxide layers of the second MOS transistor and the third MOS transistors have a same thickness”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the same thickness based on Jeong’s disclosure, in para 0034 where the ranges are approximately 15-28 A and 30-40 A respectively, to further refine the electrical characteristics of the second and third MOS transistors. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Inre Boesch, 617 F.2d 272,205USPQ 215 (CCPA 1980).
(claim 2) para 0034.
(claim 4) Fig. 4; a fourth MOS transistor (101; para 0034 … approximately 15-28 A for gate oxide 41 of the access transistor); a gate oxide layer (41); a gate (Fig. 4D in view of gate shown in Fig. 3I).
(claims 5 and 6) para 0034 (as in the rationale of claim 1 above).
(claims 7 and 8) para 0033; DRAM.
(claim 9) para 0005-0007, 103 logic transistor.
(claims 14 and 15) para 0035; para 0035, logic circuitry (as in the rationale of claim 1 above).
(claims 16-18) para 0035; para 0035, logic circuitry (as in the rationale of claim 1 above).
Regarding claims 3, the examiner does not give patentable weight in regards to the claim limitation stating that “wherein the gate oxide layers of the second MOS transistor and the third MOS transistor are formed in a same step in a same fabrication process platform” since such a limitation is taken to be a product-by-process limitation and is considered nonlimiting. A product by process claim is directed to the product per se, no matter how actually made. See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al, 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned" from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding claims 10-13, although Jeong does not disclose “(claim 10) wherein a gate line wide of the second MOS transistor is less than that of the first MOS transistor, and a gate line wide of the third MOS transistor is less than that of the first MOS transistor; (claim 11) wherein the gate line wide of each of the second MOS transistor and the third MOS transistor range from 0.05 to 10.00 µm; (claim 12) wherein a gate line wide of the second MOS transistor is less than that of the first MOS transistor, and greater than that of the fourth MOS transistor; and a gate line wide of the third MOS transistor is less than that of the first MOS transistor, and greater than that of the fourth MOS transistor; (claim 13) wherein the gate line wide of each of the second MOS transistor and the third MOS transistor range from 0.05 to 10.00”, ”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the particular width relationships of the first-fourth transistor gate lines of Jeong to further refine the electrical characteristics as desired for the specific transistors. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Allowable Subject Matter
Claims 19 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 19 stating “forming a gate oxide layer of a first MOS transistor, thinning the formed gate oxide layer in regions where a second MOS transistor and a third MOS transistor are to be formed to simultaneously form a gate oxide layer of the second MOS transistor and a gate oxide layer of the third MOS transistor”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
Prosecution Insights