DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-11 are pending in the application and are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims.
“a peripheral circuit area including a first power supply line, a second power supply line provided on the substrate, and a first ground line provided on the substrate; a bit cell area including a third power supply line, a fourth power supply line, and a second ground line provided on the substrate”, as Claim 1 recites – such as a single figure comprised all the above-cited limitation.
“the fourth power supply line (VVDD2) is provided in the substrate”, as Claim 7 recites.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification and Abstract
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 recites: “a peripheral circuit area including a first power supply line, a second power supply line provided on the substrate, and a first ground line provided on the substrate; a bit cell area including a third power supply line, a fourth power supply line, and a second ground line provided on the substrate”. However, the specification of the application, describing three possible layouts of power supply lines dispositions, does not teach a single disposition having both limitations in the peripheral circuit area (PCA) and in the bit cell area (BCA).
In order to remind power lines dispositions taught by the specification of the current application, three taught dispositions layouts (Figs. 3 4, and 5) are reproduced below.
Fig. 3
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Fig. 4
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Fig. 5
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The above-cited first limitation of Claim 1, with its second power supply line VVDD1 and first ground line VSS1 disposed on a substrate (e.g., in a “Mint” region) is shown only in Fig. 5, though VVDD1 and VSS1 are disposed not only on the substrate, but are also buried in the substrate (e.g., their portions are shown with identification “BRP”) – the limitation not reflected by Claim 1 or any other claim.
Regarding the above-cited second limitation, related to a bit cell area (BCA), it is not quite clear from the claim language if both - a fourth power supply line VVDD2 and the second ground line VSS2 – are on a substrate (in the Mint region) or only VSS2 is in the Mint region. However, Fig. 5 (on which the first limitation is read) has VSS2 buried in the substrate, so, the arrangement of Fig. 5 is not appropriate for the second limitation, but in Fig. 4, at least portions of VVDD2 and VSS2 are disposed in the Mint region. So, the second limitation is read on Fig. 4. But the current application does not teach a single disposition of power lines in which portions of Figs. 4 and 5 are combined and does not include a statement that they can be combined.
Claim 3, dependent on Claim 1, recites: “the second power switch circuit (PSW2) is positioned in the separating area (SPA)”. This limitation is read on Fig. 4, but not on Fig. 5.
Claim 5, dependent on Claim 1, recites: “the first power switch circuit is positioned in the separating area”. The limitation is read on Fig. 5, but it is not read on Fig. 4.
As it is shown, the specification of the application does not support limitations of Claims 1, 3, and 5.
Appropriate corrections are required.
Claim Objections
Claims 1, 2, 3, and 4 are objected to because of the following informalities: The claims recite: “plan view” using no article. Examiner suggests to use an article “a” – where “plan view” is cited a first time, and to use article “the” in all other cases.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claims 1 and 5: Claim 1 recites (lines 3-9): “a peripheral circuit area including a first power supply line, a second power supply line provided on the substrate, and a first ground line provided on the substrate; a bit cell area including a third power supply line, a fourth power supply line, and a second ground line provided on the substrate”.
As is explained in the objection to the specification, the combined recitation is unclear, since a portion of the recitation is read on one embodiment of disposition of power and ground lines (e.g., on the embodiment of Fig. 5), and another portion is read on another embodiment (on the embodiment of Fig. 4), while the specification does not teach that different embodiments could be combined.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971),
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation of Claim 1 is interpreted such as to be read on Fig. 5: “a peripheral circuit area including a first power supply line, a second power supply line with at least a portion provided on the substrate, and a first ground line with at least a portion provided on the substrate; a bit cell area including a third power supply line, a fourth power supply line, and a second ground line”, e.g., the specific limitations related to BCA shown in Fig. 4 are excluded. Limitations related to “portions” are added to make Claim 6 clearer, as is explained below.
With such interpreted Claim 1, Claim 5 is fully read on Claim 1.
In re Claim 3: In view of the interpretation of Claim 1 (created for the embodiment of Fig. 5), Claim 3 cannot depend on Claim 1, since Claim 3 has a limitation that is read on the embodiment of Fig. 4: “the second power switch circuit is positioned in the separating area”.
Appropriate correction is required to clarity the claim language.
For this Office Action, Claim 3 is interpreted as an independent claim:
Claim 3. A semiconductor device comprising:
a substrate;
a peripheral circuit area including a first power supply line, a second power supply line, and a first ground line;
a bit cell area including a third power supply line, a fourth power supply line and a second ground line, portions of which are provided on the substrate;
a separating area positioned between the bit cell area and the peripheral circuit area in a plan view;
a first power switch circuit connected to the first power supply line, the second power supply line, and the first ground line; and
a second power switch circuit connected to the third power supply line, the fourth power supply line, and the second ground line, wherein
the first power switch circuit includes a first switch transistor electrically connected between the first power supply line and the second power supply line, and wherein
the second power switch circuit includes a second switch transistor electrically connected between the third power supply line and the fourth power supply line is positioned in the separating area in the plan view”.
In re Claim 4: Claim 4 (dependent on Claim 3) has a limitation: “the second ground line is electrically connected to the second power switch circuit through the second ground line provided in the separating area”. The recitation is unclear, since an original Claim 3, as well as Claim 3 as interpreted by the current Office Action, do(es) not recite two second ground lines, and the application does not teach two second ground lines (for one cell).
In view of interpretation of Claim 3, citing that only a portion of the second ground line is disposed on the substrate, for this Office Action, the above-cited limitation of Claim 4 is interpreted as: “the second ground line is electrically connected to the second power switch circuit through the second ground line portion provided in the separating area”.
In re Claim 6: Claim 6, dependent on Claim 1, recites: “the first ground line is electrically connected to the first power switch circuit through the first ground line provided in the separating area”. The recitation is unclear for a reason similar to that shown for Claim 4. Appropriate correction is required to clarify the claim language.
For this Office Action, based on the interpretation of Claim 1, the cited limitation of Claim 6 is interpreted as: “the first ground line is electrically connected to the first power switch circuit through the first ground line portion provided in the separating area”.
In re Claim 10: Claim 10 recites: “the second power switch circuit includes a control circuit to control the second switch transistor”. The recitation is unclear, in view of dependency on Claim 8, which recites “a plurality of second power switch circuits”, while Claim 10 does not clarify which one of the plurality is cited with article “the”.
Appropriate correction is required to clarify the claim language.
For this Office Action, Claim 10 is interpreted as being dependent on Claim 1, which recites one second power switch and one second switch transistor. Accordingly, the recitation of Claim 10: “the one direction”, is interpreted as: “one direction”.
In re Claim 11: Claim 11 recites: “the second power switch circuit includes a control circuit to common control all of the plurality of second switch transistors”. The recitation is unclear, since Claim 11 depends on Claim 8, which recites “a plurality of second power switch circuits”, while Claim 11 does not clarify which one of the plurality is cited with article “the”.
Appropriate correction is required to clarify the claim language.
For this Office Action, Claim 11 is interpreted as being dependent on Claim 1; in addition, in order to comply with paragraph 0093 of the published application as related to Fig. 12F (on which the recitation of Claim 11 is read), the cited recitation was interpreted as: “the second power switch circuit is one of a plurality of second power switch circuits, and all these second power switch circuits are controlled by a common control circuit”.
In re Claims 2 and 7-9: Claims 2 and 7-9 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2016/0322097) in view of Hiromi (JP 2005259879) and Aoki (US 2007/0045770).
In re Claim 1, Shin teaches a semiconductor device comprising (Fig. 3):
a substrate (paragraph 0090);
a peripheral circuit area 220 (paragraph 0098) including a first power supply line VDD (paragraph 0061), and a first ground line GND (e.g., its portion connected to 220, paragraph 0062);
a second power supply line VVDD_L (paragraph 0061)
a bit cell area 210 (paragraph 0099) including a third power supply line VDDH (paragraph 0063), and a second ground line GND – as a portion connected to 210 (the limitation “provided on the substrate” – is omitted from consideration, e.g., as interpreted);
a separating area positioned between the bit cell area 210 and the peripheral circuit area 220 (as shown in Fig. 3) in plan view;
a power switch circuit for Logic Block 100 (paragraph 0060) that comprises components 400 (generating a control signal for a switch transistor 300, paragraphs 0061, 0064, 0067, 0071) and the switch transistor 300, the power switch circuit being connected to the first power supply line VDD, the second power supply line VVDD_L, and the first ground line GND (as in Fig. 3), the power switch circuit includes a switch transistor 300 electrically connected between the first power supply line and the second power supply line.
Shin does not teach that the first ground line is provided on the substrate, that the peripheral circuit includes a second power supply line, at least partially provided on the substrate and that the bit cell area comprises a fourth power supply line. Shin further does not teach that the peripheral circuit area comprises a first switch power circuit -similar to that of the power switch circuit provided for a Logic Block 100 - and comprising a first power switch connected between the first and second power lines, and Shin does not teach a second power switch circuit connected to the third power supply line, the fourth power supply line, and the second ground line and comprising a second switch connected between the third and fourth power supply lines.
Hiromi teaches that in order to reduce a leakage current for a circuit connected to power lines, a switching circuit shall be inserted between the circuit and its power line, the switching circuit comprising a transistor-switch that receives a control signal from a corresponding control circuit (Abstract, background, and page 5 – underlined sections).
Aoki teaches (Figs. 3-4, paragraphs 0034-0035) that that a power supply line VDD and a ground line GND are disposed on substrate (in which source and drain regions of MOSFETs P3 and N3 are disposed).
Shin, Hiromi, and Aoki are directed to analogous arts related to circuits comprised power lines, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Shin device in view of Hiromi and Aoki devices, since they are from the same field of endeavor, and Hiromi and Aoki created successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin device by connecting his peripheral circuit and his bit cell circuit to their respective power line through corresponding first and second power circuits, the first power switch circuit being connected to the first and second power lines (identical to those used for the logic device) and to the ground line and comprising a first power switch transistor inserted between the first and second power lines; the second power switch circuit connected to the third power line, the second ground line and to be created fourth power line, where the second power switch transistor is connected between the third and fourth power lines, creating by that a device with a circuit shown in Annotated Modified Fig. 3 (showing only first and second power switches, but not showing corresponding circuits – similar to 400 for sending signals to the first and second power switches), where it is desirable to limit leakage currents in power lines to the memory structure and to the peripheral circuit.
Annotated Modified Fig. 3
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(Note that devices with power switch circuits provided between power (ground) lines and various components connected to power lines are well-known in the art, and the examples may include at least Sasaki et al. (US 2008/0239780), as well as power switches connected between two power lines as in Takeno, US 2021/0210468, and/or Karou, US 2009/0295463).
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to further modify the Shin/Hiromi device by disposing the second power supply line and the first ground line on the substrate, per Aoki, in order to enable dispositions of the power lines.
As far as the claims are understood, Claims 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Hiromi, Aoki, and Yamaoka et al. (US 2018/0158511).
In re Claim 3 (as interpreted), Shin teaches a semiconductor device comprising (Fig. 3):
a substrate (paragraph 0090);
a peripheral circuit area 220 (paragraph 0098) including a first power supply line VDD (paragraph 0061), and a first ground line GND (e.g., its portion connected to 220, paragraph 0062);
a second power supply line VVDD_L (paragraph 0061)
a bit cell area 210 (paragraph 0099) including a third power supply line VDDH (paragraph 0063), and a second ground line GND – as a portion connected to 210 (the limitation “provided on the substrate” – is omitted from consideration, e.g., as interpreted);
a separating area positioned between the bit cell area 210 and the peripheral circuit area 220 (as shown in Fig. 3) in plan view;
a power switch circuit for Logic Block 100 (paragraph 0060) that comprises components 400 (generating a control signal for a switch transistor 300, paragraphs 0061, 0064, 0067, 0071) and the switch transistor 300, the power switch circuit being connected to the first power supply line VDD, the second power supply line VVDD_L, and the first ground line GND (as in Fig. 3), the power switch circuit includes a switch transistor 300 electrically connected between the first power supply line and the second power supply line.
Shin does not teach that the peripheral circuit includes a second power supply line and that the bit cell area comprises a fourth power supply line, where the fourth and ground power lines are positioned on the substrate. Shin further does not teach that the peripheral circuit area comprises a first switch power circuit - similar to that of the power switch circuit provided for a Logic Block 100 - and comprising a first power switch connected between the first and second power lines, and Shin does not teach a second power switch circuit connected to the third power supply line, the fourth power supply line, and the second ground line and comprising a second switch connected between the third and fourth power supply lines. Accordingly, Shin does not teach that the second power switch circuit is positioned in the separating area in the plan view
Hiromi teaches that in order to reduce a leakage current for a circuit connected to power lines, a switching circuit shall be inserted between the circuit and its power line, the switching circuit comprising a transistor-switch that receives a control signal from a corresponding control circuit (Abstract, background, and page 5 – underlined sections).
Aoki teaches (Figs. 3-4, paragraphs 0034-0035) that that a power supply line VDD and a ground line GND are disposed on substrate (in which source and drain regions of MOSFETs P3 and N3 are disposed).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin device by connecting his peripheral circuit and his bit cell circuit to their respective power line through corresponding first and second power circuits, the first power switch circuit being connected to the first and second power lines (identical to those used for the logic device) and to the ground line and comprising a first power switch transistor inserted between the first and second power lines; the second power switch circuit connected to the third power line, the second ground line and to be created fourth power line, where the second power switch transistor is connected between the third and fourth power lines, creating by that a device with a circuit shown in Annotated Modified Fig. 3, where it is desirable to limit leakage currents in power lines to the memory structure and to the peripheral circuit.
It would further have been obvious for one of ordinary skill in the art before the effective date of filing the application to dispose the fourth power line and the second ground line on the substrate (per Aoki), in order to enable dispositions of these lines.
Shin/Hiromi/Aoki does not teach that the second power switch is positioned in the separation area (between the peripheral circuit area and a bit cell area) in the plan view.
Yamaoka teaches (Fig. 8, paragraph 0040) that at least a portion of a power switch SLSW (shown as SW1 in Fig. 1) is positioned in a separation area between a bit cell area of SRAM (MA) and a peripheral circuit AMP (being a sense amplifier for MA, paragraph 0039).
Shin/Hiromi/Aoki and Yamaoka teach analogous arts directed to incorporating a power switch circuit within two portions of a power line powering a circuit, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Shin/Hiromi/Aoki device (shown in Annotated Modified Fig. 3) in view of the >Yamaoka’ teaching, since they are from the same field of endeavor, and Yamaoka created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin/Hiromi/Aoki device by depositing its second power switch in the separation area, if it is desirable to utilize the separation area.
In re Claim 5, Shin/Hiromi/Aoki teaches the semiconductor device of Claim 1 as cited above, including the first power switch circuit, but does not teach that the first power switch circuit is positioned in the separating area in (the) plan view.
Yamaoka teaches (Fig. 8, paragraph 0040) that at least a portion of a power switch SLSW (shown as SW1 in Fig. 1) is positioned in a separation area between a bit cell area of SRAM (MA) and a peripheral circuit AMP (being a sense amplifier for MA, paragraph 0039).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin/Hiromi/Aoki device of Claim 1 by depositing the first power switch in the separation area, if it is desirable to utilize the separation area.
As far as the claims are understood, Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shin/Hiromi/Aoki in view of Kobayashi (US 2010/0327452).
In re Claim 7, Shin/Hiromi/Aoki teaches the semiconductor device of Claim 1 as cited above, including the fourth power supply line, but does not teach that the fourth power supply line is provided in the substrate.
Kobayashi teaches (Figs. 1B-1C, paragraphs 0110-0115) a power supply line 14a disposed in a substrate 1.
Shin/Hiromi/Aoki and Kobayashi teach analogous arts directed to semiconductor devices incorporating power lines, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Shin/Hiromi/Aoki device in view of the Kobayashi device, since they are from the same field of endeavor, and Kobayashi created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin/Hiromi/Aoki device by disposing the fourth power supply line in the substrate, in order to enable its disposition.
As far as the claims are understood, Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shin/Hiromi/Aoki in view of Nii et al. (US 2005/0162919).
In re Claim 8, Shi/Hiromi/Aoki teaches the semiconductor device of Claim 1 as cited above, including the second power switch connected to the bit (memory) cell array, but does not teach a plurality of second power switch circuits arranged along one direction.
Nii teaches (Fig. 2) a plurality of second power switch circuits 21A+22A, 23A+24A (with corresponding control signals CS, paragraphs 0066-0068), each circuit connected to a corresponding column of memory cells.
Shin/Hiromi/Aoki and Nii teach analogous arts directed to semiconductor devices comprised memories and connected to power lines through switches, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Shin/Hiromi/Aoki device in view of the Nii device, since they are from the same field of endeavor, and Nii created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin/Hiromi/Aoki device by incorporating into the device a plurality of second power switches, each connected to a column of bit cells of the array, if such arrangement is beneficial for reducing power consumption and leakage current during charging/discharging of a bit line (Nii, paragraph 0011).
In re Claim 9, Shin/Hiromi/Aoki/Nii teaches the semiconductor device of Claim 8 as cited above, with Nii teaching the plurality of second power switch circuits.
Shin/Hiromi/Aoki/Nii further teaches (Nii, Fig. 2) that the plurality of second power switch circuits are arranged adjacent to each other.
In re Claim 11, Shin/Hiromi/Aoki teaches the semiconductor device of Claim 1 as cited above, but does not teach a plurality of second power switches that are controlled by a single control circuit.
Nii teaches (Fig. 2, paragraphs 0066-0069) a plurality of that the second power switches 21A-24A (each connected to a column of a memory array) where all second power switches are controlled by one control circuit setting control signals CS[i].
t would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Shin/Hiromi/Aoki device by incorporating into the device a plurality of second power switches, each connected to a column of bit cells of the array, if such arrangement is beneficial for reducing power consumption and leakage current during charging/discharging of a bit line (Nii, paragraph 0011).
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to use for all this plurality of second power control switches a single control circuit (per Nii), in order to simplify the device by limiting additional control circuits.
Allowable Subject Matter
Claims 2, 4, 6, and 10 contain allowable subject matter.
Reason for Indicating Allowable Subject Matter
Re Claim 2: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of claim 2 as: “the peripheral circuit area includes a plurality of first ground lines each extending in a first direction in plan view, wherein
the bit cell area includes a plurality of second ground lines each extending in the first direction”, in combination with all limitations of Claim 1, on which Claim 23 depends
Re Claim 4: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitations of Claim 4 as: “the fourth power supply line extends from the bit cell area to the separating area using an interconnect layer above the substrate, and wherein the second ground line is electrically connected to the second power switch circuit through the second ground line provided in the separating area using the interconnect layer above the substrate”, in combination with all limitations of Claim 3, on which Claim 4 depends.
Re Claim 6: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 6 as: “the first power supply line is electrically connected to a power supply line provided in the separating area using the interconnect layer above the substrate, and wherein the first ground line is electrically connected to the first power switch circuit through the first ground line provided in the separating area using the interconnect layer above the substrate”, in combination with all limitations of Claims 1 and 5, on which Claim 6 depends. .
Re Claim 10: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 10 as: “the control circuit is arranged on both sides of the second switch transistor in one direction”, in combination with all limitations of claim 1, on which Claim 10 depends
The prior arts of record, in addition to the prior arts cited by the current Office Action above, also include: Okamoto et al. (US 2019/0081029), Deng (US 2013/0294149), and Ohtou et al. (US 2018/0151494).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 04/14/26
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