DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed March 12, 2024.
Claims 1-20 are pending. Claims 1, 17 and 20 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 April 18, 2024.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on March 12, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 11 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo et al. (U.S. 2015/0049545; hereinafter “Jo”).
Regarding independent claim 1, Jo discloses a method of programming data in a nonvolatile memory device (see Abstract), the method comprising:
setting a state ordering to a first state ordering (“default state ordering,” see page 1, par. 0005), the state ordering representing a relationship between a plurality of states and data values of multi-bit data (see page 3, par. 0056-0057), each memory cell of a plurality of memory cells of the nonvolatile memory device being programmed to have one of the plurality of states (see page 3, par. 0056-0057);
performing, based on the first state ordering, a program operation on target memory cells of the plurality of memory cells (see Abstract);
swapping the state ordering from the first state ordering to a second state ordering different from the first state ordering (“converting all or part of the state data…from a default state ordering to another state ordering,” see Abstract);
performing, based on the second state ordering, the program operation on the target memory cells (“performing a (N+1)th program loop based on the converted state data,” see Abstract);
re-swapping the state ordering from the second state ordering to the first state ordering (Fig. 9: converter state ordering is back to the default state ordering); and
performing, based on the first state ordering, the program operation on the target memory cells (Fig. 9: Fine PGM).
Regarding claim 2, Jo discloses wherein the swapping of the state ordering from the first state ordering to the second state ordering comprises:
determining whether the program operation is performed with respect to a first state from among the plurality of states (see page 4, par. 0075), and
changing, based on determining that the program operation is performed with respect to the first state, the state ordering from the first state ordering to the second state ordering (see page 4, par. 0075-0076).
Regarding claim 3, Jo discloses wherein, in the first state ordering, the first state corresponds to a first data value, and a second state different from the first state corresponds to a second data value different from the first data value, and
wherein, in the second state ordering, the first state corresponds to the second data value, and the second state corresponds to the first data value (Fig. 6 shows default state ordering wherein some data values are logic 1 and others logic 0, and a converted state ordering showing changes of some data values from 1 to 0 and from 0 to 1).
Regarding claim 4, Jo discloses wherein the plurality of states comprises an erase state and a plurality of program states (see Fig. 9), and
wherein the plurality of program states comprises the first state and the second state (see Figs. 3 and 9).
Regarding claim 6, Jo discloses wherein the re-swapping of the state ordering from the second state ordering to the first state ordering comprises:
determining whether the program operation is performed with respect to a second state from among the plurality of states, the second state being different from the first state (Fig. 12: step S310), and
changing, based on determining that the program operation is performed with respect to the second state, the state ordering from the second state ordering to the first state ordering (Fig. 12: step S320).
Regarding claim 10, Jo discloses setting the state ordering based on state data stored in a plurality of latches of a plurality of page buffers of the nonvolatile memory device (see Figs. 1-2, see also pages 2-3, par. 0039 and 0046).
Regarding claim 11, Jo discloses determining the first state ordering and the second state ordering (Fig. 10: step S110-S130).
Regarding claim 16, Jo discloses wherein each of the plurality of memory cells stores data having two or more bits (see page 3, par. 0057).
Regarding independent claim 17, Jo discloses a nonvolatile memory device (see Abstract), comprising:
a memory cell array (Fig. 1: 110) comprising a plurality of memory cells (Fig. 1: MCs), each memory cell of the plurality of memory cells being programmed to have one of a plurality of states (see page 3, par. 0056-0057);
a page buffer circuit configured to control the plurality of memory cells (Fig. 1: 130), the page buffer circuit comprising a plurality of page buffers (Fig. 1: PBs) configured to set a state ordering based on state data (see page , par. 0054), the state ordering representing a relationship between the plurality of states and data values of multi-bit data (see page 3, par. 0056-0057); and
a control circuit (Fig. 1: 140) configured to:
set the state ordering to a first state ordering (“default state ordering,” see page 1, par. 0005);
perform a program operation on target memory cells based on the first state ordering (see Abstract);
swap the state ordering from the first state ordering to a second state ordering different from the first state ordering (“converting all or part of the state data…from a default state ordering to another state ordering,” see Abstract);
perform the program operation on the target memory cells based on the second state ordering (“performing a (N+1)th program loop based on the converted state data,” see Abstract);
re-swap the state ordering from the second state ordering to the first state ordering (Fig. 9: converter state ordering is back to the default state ordering); and
perform the program operation on the target memory cells based on the first state ordering (Fig. 9: Fine PGM).
Regarding claim 18, Jo discloses wherein each of the plurality of page buffers comprises:
a sense latch configured to store data programmed in a memory cell of the plurality of memory cells coupled to a corresponding bitline (see page 3, par. 0048);
data latches configured to store the state data corresponding to a corresponding state to be programmed during the program operation (see page 3, par. 0049);
a cache latch configured to receive program data to be programmed during the program operation, and to transmit the program data to the data latches (see page 3, p ar. 0050); and
a precharge circuit configured to precharge the corresponding bitline during the program operation (see page 3, par. 0047).
Regarding claim 19, Jo discloses wherein the control circuit is further configured to swap the state ordering by changing at least a portion of the state data in the data latches (see Abstract).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (U.S. 2015/0049545; hereinafter “Jo”) in view of Kim et al. (U.S. 2020/0319953; hereinafter “Kim”).
Regarding claim 7, Jo discloses the limitations with respect to claim 1.
Furthermore, Jo teaches wherein the program operation comprises a plurality of program loops (see Abstract),
wherein the plurality of program loops comprises a first program loop to an N-th program loop, where N is a positive integer greater than or equal to two (see Abstract),
wherein the re-swapping of the state ordering from the second state ordering to the first state ordering is performed during a K-th program loop subsequent to the first program loop, where K is a positive integer greater than or equal to two and less than or equal to N (see page 4, par. 0071 and 0080).
However, Jo is silent with respect to wherein the swapping of the state ordering from the first state ordering to the second state ordering is performed during the first program loop.
Kim teaches the swapping of the state ordering from the first state ordering to the second state ordering is performed during the first program loop (see page 8, par. 0108).
Since Kim and Jo are from the same field of endeavor, the teachings described by Kim would have been recognized in the pertinent art of Jo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim with the teachings of Jo for the purpose of improve program performance, see Kim’s page 1, par. 0004.
Regarding claim 8, Jo in combination with Kim teaches the limitations with respect to claim 7.
Furthermore, Kim teaches wherein each of the plurality of program loops comprises a program execution interval during which a program voltage is applied to the target memory cells, and a verification interval during which a program verification voltage is applied to the target memory cells (see Figs. 7A-7B), and
wherein the swapping of the state ordering from the first state ordering to the second state ordering is performed during the program execution interval of the first program loop (see page 8, par. 0108).
Regarding claim 9, Jo in combination with Kim teaches the limitations with respect to claim 7.
Furthermore, Jo teaches wherein each of the plurality of program loops comprises a program execution interval during which a program voltage is applied to the target memory cells, and a verification interval during which a program verification voltage is applied to the target memory cells (see Abstract and Fig. 5), and
wherein the re-swapping of the state ordering from the second state ordering to the first state ordering is performed during the verification interval of the K-th program loop (see page 4, par. 0071 and 0080).
Regarding independent claim 20, Jo teaches a method of programming data in a nonvolatile memory device (see Abstract), the method comprising:
setting a state ordering to a first state ordering (“default state ordering,” see page 1, par. 0005), the state ordering representing a relationship between a plurality of states and data values of multi-bit data (see page 3, par. 0056-0057), each memory cell of a plurality of memory cells of the nonvolatile memory device being programmed to have one of the plurality of states (see page 3, par. 0056-0057);
performing, based on the first state ordering, a program operation on target memory cells of the plurality of memory cells (see Abstract);
swapping, based on the program operation being performed with respect to a first state from among the plurality of states, the state ordering from the first state ordering to a second state ordering different from the first state ordering (“converting all or part of the state data…from a default state ordering to another state ordering,” see Abstract);
performing, based on the second state ordering, the program operation on the target memory cells (“performing a (N+1)th program loop based on the converted state data,” see Abstract);
re-swapping, based on the program operation being performed with respect to a second state from among the plurality of states that is different from the first state, the state ordering from the second state ordering to the first state ordering (Fig. 9: converter state ordering is back to the default state ordering); and
performing, based on the first state ordering, the program operation on the target memory cells (Fig. 9: Fine PGM),
wherein, in the first state ordering, the first state corresponds to a first data value, and the second state corresponds to a second data value different from the first data value (Fig. 6 shows default state ordering wherein some data values are logic 1 and others logic 0, and a converted state ordering showing changes of some data values from 1 to 0 and from 0 to 1),
wherein, in the second state ordering, the first state corresponds to the second data value, and the second state corresponds to the first data value (Fig. 6 shows default state ordering wherein some data values are logic 1 and others logic 0, and a converted state ordering showing changes of some data values from 1 to 0 and from 0 to 1),
wherein the program operation comprises a plurality of program loops (see Abstract),
wherein the plurality of program loops comprises a first program loop to an N-th program loop, where N is a positive integer greater than or equal to two (see Abstract),
wherein the re-swapping of the state ordering from the second state ordering to the first state ordering is performed during a K-th program loop subsequent to the first program loop, where K is a positive greater than or equal to two and less than or equal to N (see page 4, par. 0071 and 0080), and
wherein the first state ordering and the second state ordering are determined such that a second total time required for the program operation based on the second state ordering is shorter than a first total time required for the program operation based on the first state ordering (see page , par. 0042 and 0044).
However, Jo is silent with respect to wherein the swapping of the state ordering from the first state ordering to the second state ordering is performed during the first program loop.
Kim teaches swapping of the state ordering from the first state ordering to the second state ordering is performed during the first program loop (see page 8, par. 0108).
Since Kim and Jo are from the same field of endeavor, the teachings described by Kim would have been recognized in the pertinent art of Jo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim with the teachings of Jo for the purpose of improve program performance, see Kim’s page 1, par. 0004.
Allowable Subject Matter
Claims 5 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, there is no teaching or suggestion in the prior art of record to provide the recited first state ordering, a third state different from the first state and the second state corresponds to a third data value different from the first data value and the second data value, and a fourth state different from the first state, the second state, and the third state corresponds to a fourth data value different from the first data value, the second data value, and the third data value, and wherein, in the second state ordering, the third state corresponds to the fourth data value, and the fourth state corresponds to the third data value.
With respect to claim 12, there is no teaching or suggestion in the prior art of record to provide the recited step of determining the first state ordering and the second state ordering based on at least one of a total number of data transfers in which data is transferred between the plurality of latches during the program operation and a total time required for the program operation.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recite steps of swapping the state ordering from the second state ordering to a third state ordering different from the first state ordering and the second state ordering, performing, based on the third state ordering, the program operation on the target memory cells, re-swapping the state ordering from the third state ordering to the second state ordering, and performing, based on the second state ordering, the program operation on the target memory cells.
Conclusion
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825