DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/27/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2 and 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hasko (US 8,972,755 B1) and further in view of Wang (US 9,786,356 B2).
Claim 1: Hasko teaches a method comprising:
supplying, via a first voltage regulator, a first supply voltage to control path circuitry configured to manage a data path of a first voltage domain configured to operate at the first supply voltage (e.g. Fig. 1B; col. 5, ll. 13–25 – first voltage regulator 101(1) supplies first operational circuit module 102(1), which can be a controller/CPU);
supplying, via a second voltage regulator, a second supply voltage to data path circuitry of a second voltage domain configured to operate in a voltage zone, wherein the data path circuitry forms the data path (e.g. Fig. 1B; col. 5, ll. 20–25 – second regulator 101(2) supplies second operational circuit module 102(2). “Voltage zone” implied by VDDMIN/VDDMAX; col. 7, ll. 63–67; Fig. 5); and
altering the second supply voltage to an altered supply voltage based on the change in the error characteristic, wherein the second supply voltage and the altered supply voltage are different voltages included in the voltage zone (e.g. Hasko teaches altering supply voltage based on performance indicator. See col. 4, ll. 60–67; Fig. 5. Voltage zone is maintained (VDDMIN/VDDMAX).
Not explicitly taught by Hasko is detecting a change in an error characteristic of data associated with the second voltage domain. However, Wang teaches a memory device (e.g., SRAM) with error detection circuitry (parity/ECC) that counts errors in accessed data and adjusts the supply voltage based on the number of errors – increasing the voltage when the error count exceeds a threshold (see Fig. 1; col. 8, ll. 20–30; col. 10, ll. 40–55). Wang further teaches that the target voltage can be updated during the operational life of the device to compensate for aging, and that a bitmap of voltage-frequency pairs can be stored and used for runtime voltage selection (see col. 1, ll. 55–60; col. 12, ll. 25–35).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention, seeking to implement the SRAM performance monitoring suggested by Hasko, would have naturally looked to Wang’s concrete, well-known technique of using error information to scale voltage. Combining Hasko’s dual-regulator, multi-domain architecture with Wang’s error-based voltage adjustment would have been a predictable optimization; replacing one on-chip performance metric (ring oscillator speed) with another equally conventional metric (memory error rate) to achieve the same goal: dynamic reduction of voltage margins while maintaining reliability.
Claim 2: Hasko and Wang teach the method of claim 1, but fail to teach that the error characteristic is a bit error rate (BER) of the data. However, Wang determines a number of errors in accessed data (col. 10, ll. 55–60; col. 11, ll. 30–35). Computing a bit error rate from that count is a routine, obvious mathematical operation. Therefore, one of ordinary skill would understand that the error count, normalized by the number of bits read, is a bit error rate.
Claim 5: Hasko and Wang teach the method of claim 1, but fail to teach that the first supply voltage is higher than the second supply voltage. However, Hasko teaches independent voltage regulators for different domains (Fig. 1B). It does not specify which voltage is higher; however, it is a matter of design choice depending on the circuit requirements (e.g., control logic may operate at a higher voltage than memory). Such a choice would have been obvious to a skilled artisan.
Claim 6: Hasko and Wang teach the method of claim 1, wherein the voltage zone is defined by an upper voltage and a lower voltage. For instance, Hasko expressly teaches that the AVS module checks whether VDD is below VDDMIN and above VDDMAX before adjusting voltage (col. 7, ll. 63–67; Fig. 5, steps S516, S522). This defines a voltage zone.
Claim 7: Hasko and Wang teach the method of claim 6, but fail to teach that the lower voltage, the upper voltage, or both, are variable. However, Hasko’s VDDMIN and VDDMAX are described as predetermined, but Wang teaches that target voltage levels for each operating frequency are determined during test processes and can be updated over the device’s life (col. 9, ll. 20–35; col. 13, ll. 25–40). Updating target voltages necessarily implies that the effective lower bound (minimum voltage for reliable operation) is variable. It would have been obvious to apply Wang’s adaptive, per-frequency voltage determination to Hasko’s voltage-zone concept, thereby making the zone boundaries variable. Obvious over Hasko in view of Wang.
Claim 8: Hasko and Wang teach the method of claim 7, but fail to teach that the lower voltage varies based on a type of the data, an operational temperature of the apparatus, an age of the apparatus, a variation in a nominal voltage of the voltage regulator, or any combination thereof. However, Wang teaches that the guard band voltage component (which can be added to the test voltage to set the target voltage) may be based on temperature, workload, operating mode, operating frequency, etc. (col. 11, ll. 55–67; col. 12, ll. 1–5). Wang also teaches that target voltages are updated to compensate for aging (col. 9, ll. 20–35; col. 13, ll. 25–40). Thus Wang teaches variation based on temperature and age. Variation based on type of data or nominal voltage variation is not explicitly taught, but the claim requires only “any combination thereof”; the combination therefore teaches at least part of the limitation, and the remainder would have been obvious design refinements.
As per claim 9, the claimed features are rejected similarly to claim 1 above. Negatively correlated” reasonably means that increasing the error characteristic implies increasing the supply voltage and decreasing the error characteristic implies decreasing the supply voltage. Or voltage is adjusted in the opposite direction of acceptable error margin. Wang teaches that if number of errors increases beyond threshold, then increase the voltage. And if errors are below threshold then operate at lower voltage. Thus, this establishes an inverse/negative correlation between: acceptable error margin and voltage reduction, error increase and voltage increase. Therefore, a POSITA would recognize that:
Adaptive voltage scaling systems are negative-feedback control systems.
When reliability degrades (error increases), voltage is increased.
When reliability improves (error decreases), voltage can be reduced.
This is the textbook definition of negative correlation in a feedback-controlled system. Thus, the “negatively correlated” limitation would have been obvious in view of Wang’s explicit voltage adjustment in response to detected errors.
Claim 10: Hasko and Wang teach the apparatus of claim 9, wherein the first voltage regulator is coupled to a first voltage rail in the first voltage domain, and wherein the second voltage regulator is coupled to a second voltage rail in the second voltage domain. For instance, Hasko shows each regulator supplying its respective operational circuit module. The ordinary implementation of such a connection is via a voltage rail. This is inherent in the disclosed structure.
Claim 11: Hasko and Wang teach the apparatus of claim 9, but fail to teach that the first supply voltage is equal to a nominal voltage of the first voltage regulator. However, Hasko’s first voltage regulator may or may not be adaptively controlled. If it is not adaptively controlled (or if the AVS loop is disabled), its output is its nominal voltage. Therefore, a skilled artisan would recognize that a voltage regulator’s default output is its nominal voltage.
Claim 12: Hasko and Wang teach the apparatus of claim 9, but fail to teach that comprising at least one level shifter coupled to the first voltage domain and the second voltage domain. However, it is well known in the art that when two independent voltage domains operate at different voltage levels, level shifters are required for signals that cross between domains. Implementing such standard circuitry would have been obvious to one of ordinary skill.
Claim(s) 3, 4 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hasko and Wang as applied to claim 1 above, and further in view of RAZOR: CIRCUIT-LEVEL CORRECTION OFTIMING ERRORS FORLOW-POWER OPERATION (hereinafter D3).
Claim 3: Hasko and Wang teach the method of claim 1, but fail to teach that a value of the altered supply voltage is negatively correlated to the change in the error characteristic of the data. However, such as technique was known in the art, before the effective filing date of the claimed invention, as disclosed by D3 (e.g. pages 14-15). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to make the relationship between the altered supply voltage and the change in the error characteristic negatively correlated because adaptive voltage and frequency scaling techniques in D3 routinely use feedback from performance monitors to adjust supply voltage in an adverse manner. For instance, when error rates or error characteristic increases (indicating insufficient voltage margin), known control schemes respond by increasing the supply voltage; conversely, when error rates decrease (indicating excess voltage headroom), the control loop responds by decreasing the supply voltage. This negative correlation is a predictable, well-understood control strategy for maintaining reliable circuit operation while minimizing power consumption.
Claim 4: Hasko, Wang and D3 teach the method of claim 3, wherein: the altered supply voltage is higher than the second supply voltage when the change in the error characteristic is a decrease in a value of the error characteristic; and the altered supply voltage is less than the second supply voltage when the change in the error characteristic is an increase in a value of the error characteristic (e.g. pages 14-15, D3).
As per claim 15, the claimed features are rejected similarly to claim 1 above. And the technique of altering a voltage based on detected BER was known in the art, before the effective filing date of the claimed invention, as disclosed by D3 (e.g. page 11). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to employ BER as the error characteristic in the teaching of D1 and D2, since BER is a standard, quantifiable measure of data reliability that directly reflects the effect of voltage scaling on error performance (as disclosed by D3 – page 11). Substituting BER for the generic error characteristic of D1 and D2 would have predictably resulted in improved precision and robustness of adaptive voltage control, which is nothing more than the predictable use of known technique to improve a similar device.
As per using a higher voltage supply in the first domain than the second domain, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to configure the first domain to operate at a higher supply voltage than the second domain, since it was well-known in the art, that different functional blocks on an integrated circuit are designed with different voltage requirements depending on speed, performance, and power constraints. For example, high-performance logic domains (e.g. CPU cores or high-speed processing blocks) conventionally operate at higher voltage to achieve greater speed, while peripheral or memory domains typically operate at a lower voltage to reduce power consumption and leakage. Thus, choosing the first supply voltage to be higher than the second supply voltage is nothing more than an obvious design choice to optimize performance and power efficiency in a multi voltage domain system.
Claim 16: Hasko, Wang and D3 teach the system of claim 15, wherein the first supply voltage remains substantially constant responsive to alteration of the second supply voltage to the altered supply voltage. For instance, Hasko teaches independent regulators for different domains; adjusting one regulator’s output does not affect the other. This is inherent in the architecture. Wang also adjusts the memory supply voltage independently.
Claim 17: Hasko, Wang and D3 teach the system of claim 15, wherein the errors include a quantity of correctable errors, and wherein the second voltage domain includes error correction circuitry configured to detect and correct the quantity of the correctable errors. For instance, Wang’s error detection/correction circuitry 122 includes a SECDED decoder that corrects single-bit errors (correctable) and detects double-bit errors (uncorrectable) (col. 11, ll. 15–25; col. 14, ll. 30–35).
Claim 18: Hasko, Wang and D3 teach the system of claim 17, but fail to teach a low-pass filter configured to: attenuate the quantity of correctable errors when the quantity of correctable errors exceeds a correctable error threshold; and transmit to the controller signaling that is indicative of the quantity of correctable errors when the quantity of correctable errors is less than or equal to the correctable error threshold. However, such a modification would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, because a low-pass filter for attenuating high error-rate signals before passing error metrics to a controller is a routine signal-processing technique to reduce noise and stabilize adaptive control loops. A person of ordinary skill in the art would have been motivated to use such filtering to prevent rapid or erroneous voltage adjustments due to transient spikes in correctable errors counts, yielding a more stable and reliable feedback loop.
Claim 19: Hasko, Wang and D3 teach the system of claim 15, wherein the errors include a quantity of uncorrectable errors, and wherein the second voltage domain includes: error detection circuitry configured to detect the quantity of the uncorrectable errors; and a counter to count the quantity of the uncorrectable errors. For instance, error detection circuitry 122 detects multi-bit errors (uncorrectable) (col. 11, ll. 20–25). Adjustment circuitry 130 includes a counter 132 configured to count the number of errors (col. 10, ll. 55–60).
Claim 20: Hasko, Wang and D3 teach the system of claims 19, but fail to teach further comprising a low-pass filter configured to: attenuate the quantity of uncorrectable errors when the quantity of uncorrectable errors exceeds an uncorrectable error threshold; and transmit to the controller signaling indicative of the quantity of uncorrectable errors when the quantity of uncorrectable errors is less than or equal to the uncorrectable error threshold. However, such a modification would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, because incorporation a low-pass filter for uncorrectable error signaling, analogous to correctable error filtering, would have been a simple and predictable extension to prevent spurious error spikes from destabilizing the controller’s decision-making logic.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/11/2026