DETAILED ACTION
This action is responsive to the claims filed 27 Jan 2026. Claims 1-6, 8-13 and 15-20 are pending. Claims 1, 8 and 15 are independent, and claims 7 & 14 have been cancelled.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The applicant accepted the application title change:
“CORRECTIVE READ WITH PARTIAL BLOCK OFFSET BASED ON ADJACENT WORDLINES IN A MEMORY DEVICE”
The examiner has changed the name on the application bibliography and will submit the name change as part of the Examiner’s Amendment if an allowance is granted.
Response to Amendment
The Amendment filed 27 Jan 2026 has been entered. Claims 1-6, 8-13 and 15-20 are currently pending in the application.
Response to Arguments
Applicant’s arguments filed on 27 Jan 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 102 as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The Applicant states “AHN’s AG1 group simply includes cells with low threshold voltages (including erased state cells), but this is part of a general coupling pattern classification scheme applied to all cells regardless of whether the block is partially or fully programmed.”
Response 1: The Examiner respectfully disagrees. Applicant’s argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., a partially or fully programmed block) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (see MPEP 2145 (VI).)
In this case, the claim only requires that a single memory cell be empty, which Ahn clearly teaches in the full description of figures 21 and 26. However, even if applicant had written their claim for all of the memory cells to be empty in a word line, Ahn teaches this as well – by applying the empty/erased value of AG1 to that entire word line and setting the read-correct voltage as appropriate.
Argument 2: The Applicant states “AHN’s sub- read voltage sets are selected based on individual cell coupling patterns, rather than on a determination of whether the adjacent wordline as a whole is in an erased state triggering use of a different offset value than would be used if the adjacent wordline were not in the erased state.”
Response 2: The Examiner respectfully disagrees. The applicant has only claimed that a single memory cell may be empty. As stated above, Ahn teaches that contingency and applies a distinct read-correct value to the desired cells in the case where all of the neighboring cells on the word line above and below are erased.
The Examiner further notes that MPEP 2111.03 Transitional Phrases states:
I. COMPRISING The transitional term “comprising”, which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.
II. CONSISTING OF The transitional phrase “consisting of” excludes any element, step, or ingredient not specified in the claim.
Applicant uses the transitional phrase “comprising” in the claim, thus the fact that Ahn more narrowly teaches the read-correct pattern for not only erased cells but every combination of written data in the wordlines above and below anticipates the claim as written.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by AHN, et al, U.S. Patent Application Publication 2024/0126453 (“AHN”).
Regarding claim 1, AHN teaches:
A memory device comprising: a memory array comprising a plurality of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising: (AHN, fig 2, “[0080] Referring to FIG. 2, the non-volatile memory 200 may include a memory cell array 211, a control logic 220, a voltage generator 230, a row decoder 240, and a page buffer circuit 250.”; a memory with an array of cells, controllers and voltage generators).
receiving a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of the memory array; (AHN, fig 30, “[0263] FIG. 30 is a flowchart of a read operation method, according to an embodiment. [0265] In operation Sll0, a first read operation may be performed in response to the read request provided from the host. [0266] In operation S120, the storage control may check whether the first read operation has passed. Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113.”; a memory receives a read request described in figure 30 which includes descriptive paragraphs 0263-0272; that the first data read operation has errors and then goes to a second read operation).
determining whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state; and (AHN, fig 21, 26, “[0204] FIG. 21 is a graph illustrating a method of grouping a plurality of aggressor cell groups, according to an embodiment. [0209] For example, the first aggressor cell group AG1 may include a memory cell having a threshold voltage lower than the first group determination read voltage V.gd1. [0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory can group at least three sets of memory cells into groups as shown in fig 21, here AG1 comprises all of the memory cells in the “Erased” or “1” state; additionally the system can look at adjacent wordlines above and below for the operation as shown in fig 26).
responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state: (AHN, fig 25, “[0231] FIG. 25 illustrates a table of sub-read voltage sets for a TLC, according to an embodiment. … and the number of types of sub-read voltage sets may be equal to the number of types of coupling patterns.”; a memory device with at least 3 coupling patterns from above AG1-AG3, that AG1 (the claimed erased set) can be one of the coupling patterns; that a “sub-read voltage set” based on the AG1 comprising of the “erased state” can be performed).
identifying a partial block read voltage offset value, wherein the partial block read voltage offset value is different than a plurality of full block read voltage offset values to be used to perform the corrective read operation if one or more memory cells associated with the adjacent wordline were not in the erased state; and (AHN, fig 21, 26, “[0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line WLal and a second adjacent word line WLa2. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory device with at least 3 coupling patterns between word lines: AG1-AG3, that AG2 and AG3 coupling patterns are used when the adjacent word line is in a P1-P7 programmed state (i.e. not in the erased state); that IF ALL of the adjacent wordlines in a block are empty/ erased, THEN the AG1 (empty cell) sub-read voltage set is applied to read ALL of the target memory cells; that IF some of the adjacent wordlines contain data, THEN a different sub-read voltage is applied to read those target memory cells; fig 26 shows that the word lines above and below are sampled to select the desired sub-read voltages; that the sub-read voltage set operation applies a different value for the different coupling patterns between word lines if the WLa1 is in the AG1 state than if the WLa1 contains written data) . [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset with a single erased cell) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset).
causing a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline. (AHN, fig 30, “[0267] When the first read operation has failed (No in operation S120), a second read operation may be performed in operation S130. The second read operation may be an operation of reading data based on a history read voltage set.”; a memory device that fails a first read, causes a second read process to occur at decision S120; that then identifies the “sub-read voltage set” of fig 25 based on AG1-AG3 where AG1 is the erased state of fig 21; that the system then reads the voltage using the voltages of the table in fig 25 using AG1 as the neighbor wordlines to the desired memory cell as shown in fig 26. Note: the fact that each of the memory cells, including those not in the “erase state” is not prohibited by applicant’s claim limitations).
Regarding claim 2, AHN teaches The memory device of claim 1, wherein the request to perform the corrective read operation is received from a memory sub-system controller in response to a failure of a read operation on the one or more memory cells associated with a selected wordline using the read voltage. (AHN, fig 30, “[0266] Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113. In an embodiment, the read manager 111 may determine whether the first read operation has passed, according to whether an error in the read data is correctable by the ECC circuit 113.”; an error correcting code step where the reading of data has triggered a second read operation based on a failed ECC; that the data read is from multiple wordlines as shown in figure 26).
Regarding claim 3, AHN teaches:
The memory device of claim 1, wherein determining whether the one or more memory cells associated with the adjacent wordline in the memory array are in the erased state comprises: causing the read voltage to be applied to the adjacent wordline to determine respective threshold voltages of the one or more memory cells associated with the adjacent wordline; (AHN, fig 11, 26, “[0130] In a read operation, the erase state E and the first to seventh program states E and Pl to P7 of the TLC may be determined by applying first to seventh read voltages Vrd1 to Vrd7 to the selection word line and applying the pass voltage Vpass to an unselected word line. [0138] Referring to FIG. 11, a selection word line WLs may include a plurality of selection memory cells C1 to C8. An adjacent word line WLAN may include a plurality of adjacent memory cells Cl’ to CS’. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2.”; a reading and storage of two adjacent wordlines; that the cell values of each cell are read; that the cell values are categorized as AG1,2,3; that AG1 can be all of the erased state cells).
determining whether a number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfies a threshold condition; and responsive to the number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfying the threshold condition, determining that the one or more memory cells associated with the adjacent wordline are in the erased state. (AHN, fig 11, 26, “[0136] However, if the degree of degradation of the threshold voltage distributions is high, it may be difficult to determine states E and Pl to P7 of a TLC even by using the first to seventh optimum read voltages Vrd1’ to Vrd7’. Thus, patterns coupled to selection memory cells connected to a selection word line may be classified according to a state of adjacent memory cells connected to at least one adjacent word line that is physically adjacent to the selection word line. Accordingly, it may be necessary to calculate subdivided read voltages.”; that the system may read all of the wordlines using the thresholds between data states, that the data can be classified as erased, S1-S7; that these can be grouped in AG1, 2, or 3 based on the read state).
Regarding claim 4, AHN teaches The memory device of claim 1, wherein the adjacent wordline is adjacent to the selected wordline in the memory array on a source-side of the selected wordline. (AHN, fig 26, “[0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2. The first adjacent word line Wal may be adjacent to a selection word line WLs in one direction, and the second adjacent word line WLa2 may be adjacent to the selection word line WLs in a direction opposite to the one direction.”; a device where the system reads two adjacent wordlines, one above (drain side) and below the target wordline (source side); that special cases for the bottom wordline and top wordline are also discussed).
Regarding claim 5, AHN teaches:
The memory device of claim 1, wherein, responsive to determining that the one or more memory cells associated with the adjacent wordline are not in the erased state, the control logic is to perform operations further comprising: identifying one of a plurality of full block read voltage offset values; and (AHN, fig 25, 26, 28, 30, 31, “[0232] Referring to FIG. 25, four (4) sub-read voltage sets Vsrs1, Vsrs2, Vsrs3, and Vsrs4 may be sub-read voltage sets for a TLC in which the number of types of coupling patterns is four (4). [0250] FIG. 28 shows graphs of threshold voltage distributions of selection memory cells coupled to adjacent word lines, according to an embodiment. [0251] The first threshold voltage distributions TVD1 may be, for example, threshold voltage distributions of a plurality of selection memory cells having a first coupling pattern CP1 from among the plurality of coupling patterns.”; fig 25 which shows the coupling patterns and voltage offsets for each of the coupled patterns from erased to S3; that each of these coupling offsets can be determined for a configuration of fig 26; that the distributions for multiple cases can be known in fig 28 based on coupling between the target wordline and coupled wordline).
causing the read voltage modified according to the one of the plurality of full block read voltage offset values to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; a description of flowchart in paragraphs 0274-289 inclusive; that the memory cell Valley Search (S200-S210) is used to determine the closest states and threshold voltages for each state ; that the coupling pattern (S220) is then selected between wordlines based on the newly determined thresholds; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 can be the erased state correction, and AG2, 3 can be other corrected states).
Regarding claim 6, AHN teaches The memory device of claim 5, wherein the one of the plurality of full block read voltage offset values is identified based on a threshold voltage of the one or more memory cells associated with the adjacent wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset) can be other corrected states).
Regarding claim 8, AHN teaches:
A method comprising: (AHN, fig 2, “[0080] Referring to FIG. 2, the non-volatile memory 200 may include a memory cell array 211, a control logic 220, a voltage generator 230, a row decoder 240, and a page buffer circuit 250.”; a memory with an array of cells, controllers and voltage generators).
receiving a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device; (AHN, fig 30, “[0263] FIG. 30 is a flowchart of a read operation method, according to an embodiment. [0265] In operation Sll0, a first read operation may be performed in response to the read request provided from the host. [0266] In operation S120, the storage control may check whether the first read operation has passed. Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113.”; a memory receives a read request described in figure 30 which includes descriptive paragraphs 0263-0272; that the first data read operation has errors and then goes to a second read operation).
determining whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state; and (AHN, fig 21, 26, “[0204] FIG. 21 is a graph illustrating a method of grouping a plurality of aggressor cell groups, according to an embodiment. [0209] For example, the first aggressor cell group AG1 may include a memory cell having a threshold voltage lower than the first group determination read voltage V.gd1. [0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory can group at least three sets of memory cells into groups as shown in fig 21, here AG1 comprises all of the memory cells in the “Erased” or “1” state; that the system can look at adjacent wordlines as shown in fig 26).
responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state: (AHN, fig 25, “[0231] FIG. 25 illustrates a table of sub-read voltage sets for a TLC, according to an embodiment. … and the number of types of sub-read voltage sets may be equal to the number of types of coupling patterns.”; a memory device with at least 3 coupling patterns from above AG1-AG3, that AG1 (the claimed erased set) can be one of the coupling patterns; that a “sub-read voltage set” based on the AG1 can be performed).
identifying a partial block read voltage offset value, wherein the partial block read voltage offset value is different than a plurality of full block read voltage offset values to be used to perform the corrective read operation if one or more memory cells associated with the adjacent wordline were not in the erased state; and (AHN, fig 21, 26, “[0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line WLal and a second adjacent word line WLa2. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory device with at least 3 coupling patterns between word lines: AG1-AG3, that AG2 and AG3 coupling patterns are used when the adjacent word line is in a P1-P7 programmed state (i.e. not in the erased state); that IF ALL of the adjacent wordlines in a block are empty/ erased, THEN the AG1 (empty cell) sub-read voltage set is applied to read ALL of the target memory cells; that IF some of the adjacent wordlines contain data, THEN a different sub-read voltage is applied to read those target memory cells; fig 26 shows that the word lines above and below are sampled to select the desired sub-read voltages; that the sub-read voltage set operation applies a different value for the different coupling patterns between word lines if the WLa1 is in the AG1 state than if the WLa1 contains written data) . [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset with a single erased cell) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset).
causing a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline. (AHN, fig 30, “[0267] When the first read operation has failed (No in operation S120), a second read operation may be performed in operation S130. The second read operation may be an operation of reading data based on a history read voltage set.”; a memory device that fails a first read, causes a second read process to occur at decision S120; that then identifies the “sub-read voltage set” of fig 25 based on AG1-AG3 where AG1 is the erased state of fig 21; that the system then reads the voltage using the voltages of the table in fig 25 using AG1 as the neighbor wordlines to the desired memory cell as shown in fig 26. Note: the fact that each of the memory cells, including those not in the “erase state” is not prohibited by applicant’s claim limitations).
Regarding claim 9, AHN teaches The method of claim 8, wherein the request to perform the corrective read operation is received from a memory sub-system controller in response to a failure of a read operation on the one or more memory cells associated with a selected wordline using the read voltage. (AHN, fig 30, “[0266] Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113. In an embodiment, the read manager 111 may determine whether the first read operation has passed, according to whether an error in the read data is correctable by the ECC circuit 113.”; an error correcting code step where the reading of data has triggered a second read operation based on a failed ECC; that the data read is from multiple wordlines as shown in figure 26).
Regarding claim 10, AHN teaches:
The method of claim 8, wherein determining whether the one or more memory cells associated with the adjacent wordline in the memory array are in the erased state comprises: causing the read voltage to be applied to the adjacent wordline to determine respective threshold voltages of the one or more memory cells associated with the adjacent wordline; (AHN, fig 11, 26, “[0130] In a read operation, the erase state E and the first to seventh program states E and Pl to P7 of the TLC may be determined by applying first to seventh read voltages Vrd1 to Vrd7 to the selection word line and applying the pass voltage Vpass to an unselected word line. [0138] Referring to FIG. 11, a selection word line WLs may include a plurality of selection memory cells C1 to C8. An adjacent word line WLAN may include a plurality of adjacent memory cells Cl’ to CS’. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2.”; a reading and storage of two adjacent wordlines; that the cell values of each cell are read; that the cell values are categorized as AG1,2,3; that AG1 can be all of the erased state cells).
determining whether a number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfies a threshold condition; and responsive to the number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfying the threshold condition, determining that the one or more memory cells associated with the adjacent wordline are in the erased state. (AHN, fig 11, 26, “[0136] However, if the degree of degradation of the threshold voltage distributions is high, it may be difficult to determine states E and Pl to P7 of a TLC even by using the first to seventh optimum read voltages Vrd1’ to Vrd7’. Thus, patterns coupled to selection memory cells connected to a selection word line may be classified according to a state of adjacent memory cells connected to at least one adjacent word line that is physically adjacent to the selection word line. Accordingly, it may be necessary to calculate subdivided read voltages.”; that the system may read all of the wordlines using the thresholds between data states, that the data can be classified as erased, S1-S7; that these can be grouped in AG1, 2, or 3 based on the read state).
Regarding claim 11, AHN teaches The method of claim 8, wherein the adjacent wordline is adjacent to the selected wordline in the memory array on a source-side of the selected wordline. (AHN, fig 26, “[0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2. The first adjacent word line Wal may be adjacent to a selection word line WLs in one direction, and the second adjacent word line WLa2 may be adjacent to the selection word line WLs in a direction opposite to the one direction.”; a device where the system reads two adjacent wordlines, one above (drain side) and below the target wordline (source side); that special cases for the bottom wordline and top wordline are also discussed).
Regarding claim 12, AHN teaches:
The method of claim 8, further comprising: responsive to determining that the one or more memory cells associated with the adjacent wordline are not in the erased state: identifying one of a plurality of full block read voltage offset values; and (AHN, fig 25, 26, 28, 30, 31, “[0232] Referring to FIG. 25, four (4) sub-read voltage sets Vsrs1, Vsrs2, Vsrs3, and Vsrs4 may be sub-read voltage sets for a TLC in which the number of types of coupling patterns is four (4). [0250] FIG. 28 shows graphs of threshold voltage distributions of selection memory cells coupled to adjacent word lines, according to an embodiment. [0251] The first threshold voltage distributions TVD1 may be, for example, threshold voltage distributions of a plurality of selection memory cells having a first coupling pattern CP1 from among the plurality of coupling patterns.”; fig 25 which shows the coupling patterns and voltage offsets for each of the coupled patterns from erased to S3; that each of these coupling offsets can be determined for a configuration of fig 26; that the distributions for multiple cases can be known in fig 28 based on coupling between the target wordline and coupled wordline).
causing the read voltage modified according to the one of the plurality of full block read voltage offset values to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; a description of flowchart in paragraphs 0274-289 inclusive; that the memory cell Valley Search (S200-S210) is used to determine the closest states and threshold voltages for each state ; that the coupling pattern (S220) is then selected between wordlines based on the newly determined thresholds; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 can be the erased state correction, and AG2, 3 can be other corrected states).
Regarding claim 13, AHN teaches The method of claim 12, wherein the one of the plurality of full block read voltage offset values is identified based on a threshold voltage of the one or more memory cells associated with the adjacent wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset) can be other corrected states).
Regarding claim 15, AHN teaches:
A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: (AHN, fig 2, “[0080] Referring to FIG. 2, the non-volatile memory 200 may include a memory cell array 211, a control logic 220, a voltage generator 230, a row decoder 240, and a page buffer circuit 250.”; a memory with an array of cells, controllers and voltage generators).
determining to perform a corrective read operation on one or more memory cells associated with a selected wordline of the memory device; (AHN, fig 30, “[0263] FIG. 30 is a flowchart of a read operation method, according to an embodiment. [0265] In operation Sll0, a first read operation may be performed in response to the read request provided from the host. [0266] In operation S120, the storage control may check whether the first read operation has passed. Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113.”; a memory receives a read request described in figure 30 which includes descriptive paragraphs 0263-0272; that the first data read operation has errors and then goes to a second read operation).
determining whether one or more memory cells associated with an adjacent wordline of the memory device are in an erased state; and (AHN, fig 21, 26, “[0204] FIG. 21 is a graph illustrating a method of grouping a plurality of aggressor cell groups, according to an embodiment. [0209] For example, the first aggressor cell group AG1 may include a memory cell having a threshold voltage lower than the first group determination read voltage V.gd1. [0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory can group at least three sets of memory cells into groups as shown in fig 21, here AG1 comprises all of the memory cells in the “Erased” or “1” state; that the system can look at adjacent wordlines as shown in fig 26).
responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state: (AHN, fig 25, “[0231] FIG. 25 illustrates a table of sub-read voltage sets for a TLC, according to an embodiment. … and the number of types of sub-read voltage sets may be equal to the number of types of coupling patterns.”; a memory device with at least 3 coupling patterns from above AG1-AG3, that AG1 (the claimed erased set) can be one of the coupling patterns; that a “sub-read voltage set” based on the AG1 can be performed).
identifying a partial block read voltage offset value, wherein the partial block read voltage offset value is different than a plurality of full block read voltage offset values to be used to perform the corrective read operation if one or more memory cells associated with the adjacent wordline were not in the erased state; and (AHN, fig 21, 26, “[0210] In such an example, the erase state E may belong to the first aggressor cell group AG1, the first to third program states Pl to P3 may belong to the second aggressor cell group AG2, and the fourth to seventh program states P4 to P7 may belong to the third aggressor cell group AG3. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line WLal and a second adjacent word line WLa2. [0238] Adjacent memory cells Cl’ to CS’ may be connected to the first adjacent word line WLa1. … Adjacent memory cells Cl” to CS” may be connected to the second adjacent word line WLa2.”; a memory device with at least 3 coupling patterns between word lines: AG1-AG3, that AG2 and AG3 coupling patterns are used when the adjacent word line is in a P1-P7 programmed state (i.e. not in the erased state); that IF ALL of the adjacent wordlines in a block are empty/ erased, THEN the AG1 (empty cell) sub-read voltage set is applied to read ALL of the target memory cells; that IF some of the adjacent wordlines contain data, THEN a different sub-read voltage is applied to read those target memory cells; fig 26 shows that the word lines above and below are sampled to select the desired sub-read voltages; that the sub-read voltage set operation applies a different value for the different coupling patterns between word lines if the WLa1 is in the AG1 state than if the WLa1 contains written data) . [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset with a single erased cell) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset).
sending a first corrective read command specifying the partial block read voltage offset value to the memory device to cause a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline (AHN, fig 30, “[0267] When the first read operation has failed (No in operation S120), a second read operation may be performed in operation S130. The second read operation may be an operation of reading data based on a history read voltage set.”; a memory device that fails a first read, causes a second read process to occur at decision S120; that then identifies the “sub-read voltage set” of fig 25 based on AG1-AG3 where AG1 is the erased state of fig 21; that the system then reads the voltage using the voltages of the table in fig 25 using AG1 as the neighbor wordlines to the desired memory cell as shown in fig 26. Note: the fact that each of the memory cells, including those not in the “erase state” is not prohibited by applicant’s claim limitations).
Regarding claim 16, AHN teaches The system of claim 15, wherein determining to perform the corrective read operation is based on a failure of a read operation on the one or more memory cells associated with a selected wordline using the read voltage. (AHN, fig 30, “[0266] Whether or not the first read operation passes may be determined according to whether read data is normal data and/or data including an error that is correctable by the ECC circuit 113. In an embodiment, the read manager 111 may determine whether the first read operation has passed, according to whether an error in the read data is correctable by the ECC circuit 113.”; an error correcting code step where the reading of data has triggered a second read operation based on a failed ECC; that the data read is from multiple wordlines as shown in figure 26).
Regarding claim 17, AHN teaches:
The system of claim 15, wherein determining whether the one or more memory cells associated with the adjacent wordline in the memory device are in the erased state comprises: causing the read voltage to be applied to the adjacent wordline to determine respective threshold voltages of the one or more memory cells associated with the adjacent wordline; (AHN, fig 11, 26, “[0130] In a read operation, the erase state E and the first to seventh program states E and Pl to P7 of the TLC may be determined by applying first to seventh read voltages Vrd1 to Vrd7 to the selection word line and applying the pass voltage Vpass to an unselected word line. [0138] Referring to FIG. 11, a selection word line WLs may include a plurality of selection memory cells C1 to C8. An adjacent word line WLAN may include a plurality of adjacent memory cells Cl’ to CS’. [0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2.”; a reading and storage of two adjacent wordlines; that the cell values of each cell are read; that the cell values are categorized as AG1,2,3; that AG1 can be all of the erased state cells).
determining whether a number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfies a threshold condition; and responsive to the number of the one or more memory cells associated with the adjacent wordline having respective threshold voltages that exceed the read voltage satisfying the threshold condition, determining that the one or more memory cells associated with the adjacent wordline are in the erased state. (AHN, fig 11, 26, “[0136] However, if the degree of degradation of the threshold voltage distributions is high, it may be difficult to determine states E and Pl to P7 of a TLC even by using the first to seventh optimum read voltages Vrd1’ to Vrd7’. Thus, patterns coupled to selection memory cells connected to a selection word line may be classified according to a state of adjacent memory cells connected to at least one adjacent word line that is physically adjacent to the selection word line. Accordingly, it may be necessary to calculate subdivided read voltages.”; that the system may read all of the wordlines using the thresholds between data states, that the data can be classified as erased, S1-S7; that these can be grouped in AG1, 2, or 3 based on the read state).
Regarding claim 18, AHN teaches The system of claim 15, wherein the adjacent wordline is adjacent to the selected wordline in the memory device on a source-side of the selected wordline. (AHN, fig 26, “[0237] Referring to FIG. 26, in some embodiments, the number of adjacent word lines may be two (2), and a plurality of adjacent word lines may include a first adjacent word line Wal and a second adjacent word line WLa2. The first adjacent word line Wal may be adjacent to a selection word line WLs in one direction, and the second adjacent word line WLa2 may be adjacent to the selection word line WLs in a direction opposite to the one direction.”; a device where the system reads two adjacent wordlines, one above (drain side) and below the target wordline (source side); that special cases for the bottom wordline and top wordline are also discussed).
Regarding claim 19, AHN teaches:
The system of claim 15, wherein, responsive to determining that the one or more memory cells associated with the adjacent wordline are not in the erased state, the processing device is to perform operations further comprising: identifying one of a plurality of full block read voltage offset values; and (AHN, fig 25, 26, 28, 30, 31, “[0232] Referring to FIG. 25, four (4) sub-read voltage sets Vsrs1, Vsrs2, Vsrs3, and Vsrs4 may be sub-read voltage sets for a TLC in which the number of types of coupling patterns is four (4). [0250] FIG. 28 shows graphs of threshold voltage distributions of selection memory cells coupled to adjacent word lines, according to an embodiment. [0251] The first threshold voltage distributions TVD1 may be, for example, threshold voltage distributions of a plurality of selection memory cells having a first coupling pattern CP1 from among the plurality of coupling patterns.”; fig 25 which shows the coupling patterns and voltage offsets for each of the coupled patterns from erased to S3; that each of these coupling offsets can be determined for a configuration of fig 26; that the distributions for multiple cases can be known in fig 28 based on coupling between the target wordline and coupled wordline).
sending a second corrective read command specifying the one of the plurality of full block read voltage offset values to the memory device to cause a read voltage modified according to the one of the plurality of full block read voltage offset values to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; a description of flowchart in paragraphs 0274-289 inclusive; that the memory cell Valley Search (S200-S210) is used to determine the closest states and threshold voltages for each state ; that the coupling pattern (S220) is then selected between wordlines based on the newly determined thresholds; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 can be the erased state correction, and AG2, 3 can be other corrected states).
Regarding claim 20, AHN teaches The system of claim 19, wherein the one of the plurality of full block read voltage offset values is identified based on a threshold voltage of the one or more memory cells associated with the adjacent wordline. (AHN, fig 31, “[0274] Referring to FIG. 31, in operation S200, a plurality of points may be obtained by performing a valley search operation. [0275] Operation S210 of calculating first and second voltage levels, based on the plurality of points, may be performed. [0276] In operation S220, coupling patterns of selection memory cells may be classified according to an aggressor cell group of each of adjacent memory cells. [0277] In some embodiments, operation S220 may include grouping adjacent memory cells, which may be connected to at least one adjacent word line physically adjacent to the selection word line. [0281] In operation S230, a data recovery read voltage may be calculated based on the coupling pattern and the first and second voltage levels.”; that the data recovery (S230) is then applied to each of the coupling patterns between the target wordline and aggressor wordline after the states have been grouped into AG1,2, or 3 based on their data state; that AG1 (i.e. the claimed partial block offset) can be the erased state correction, and AG2, 3 (i.e. the claimed full block read voltage offset) can be other corrected states).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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