DETAILED ACTION
This action is responsive to the claims filed 22 Jun 2026. Claims 1-6, 8-13 and 15-20 are pending. Claims 1, 8 and 15 are independent, and claims 7 & 14 have been cancelled.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The applicant accepted the application title change:
“CORRECTIVE READ WITH PARTIAL BLOCK OFFSET BASED ON ADJACENT WORDLINES IN A MEMORY DEVICE”
The examiner has changed the name on the application bibliography and will submit the name change as part of the Examiner’s Amendment if an allowance is granted.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 Jun 2026 has been entered.
18/602,960: Present App.
12,603,138 US Patent
17/823,191 Prior App.
Rationale
1. A memory device comprising: a memory array comprising a plurality of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising:
receiving a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of the memory array;
determining whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state; and
responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state:
identifying a partial block read voltage offset value, wherein the partial block read voltage offset value is different than a plurality of full block read voltage offset values to be used to perform the corrective read operation if one or more memory cells associated with the adjacent wordline were not in the erased state; and
causing a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.
1. A memory device, comprising: a memory; and a controller, configured to:
receive a read command associated with a block of the memory;
determine that a block type associated with the block is a partial block type in which at least a portion of word lines of the block are erased;
identify, based on the block type being the partial block type, one or more read voltage offsets for a read operation associated with the block; determine one or more adjusted read reference voltages associated with the block based on the one or more read voltage offsets; and
perform the read operation using the adjusted read reference voltages based on the one or more read voltage offsets.
The present application anticipates US Patent 12,603,138
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,603,138. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the present application anticipates each and every element of the published patent.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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