DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 6/15/2026 "Reply" elects without traverse and identifies claims 1-10 and 20 as being drawn to Invention I. Accordingly, Examiner has withdrawn claims 12-19 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 6/3/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung (US Pub. No. 2022/0189875).
Regarding claim 1, in FIG. 2, Sung discloses a semiconductor device, comprising: a first deck (10-1) comprising a first staircase structure extending along a first direction (FD); and a second deck (10-2) adjacent to the first deck along a second direction (VD) perpendicular to the first direction, wherein the second deck comprises a second staircase structure, and wherein the first staircase structure is adjacent to or has a gap with the second staircase structure on the first direction.
Regarding claim 2, in FIG. 2, Sung discloses that the second deck comprises a stack of conductive layers (10a-c) and isolating layers (40, paragraph [0031]) alternating with each other along the second direction, and the stack of conductive layers and isolating layers is adjacent to the first staircase structure along the second direction.
Regarding claim 3, in FIG. 2, Sung discloses that the first direction and the second direction define a first plane, wherein a first area is a projection of the first staircase structure on the first plane, wherein a second area is a projection of the second staircase structure on the first plane, and wherein the first area has the same shape as the second area.
Regarding claim 4, in FIG. 2, Sung discloses that each of the first area and the second area is a V-shaped area.
Regarding claim 5, in FIG. 2, Sung discloses that the first staircase structure comprises a first staircase substructure and a second staircase substructure, the first staircase substructure comprises first staircase steps descending along the first direction, and the second staircase substructure comprises second staircase steps ascending along the first direction.
Regarding claim 6, in FIG. 2, Sung discloses that the first deck comprises an array region (stack adjacent to STd), a wall region (unpatterned stack behind STx in SD direction), and a connection region (in contact with CNT2) comprising the first staircase structure, wherein the wall region is adjacent to the connection region along a third direction (SD) perpendicular to the first direction and the second direction, and wherein the second staircase steps ascending along the first direction are coupled to the array region via the wall region.
Regarding claim 20, in FIGs. 2 and 13, Sung discloses a system, comprising: a semiconductor device comprising: a first deck (10-1) comprising a first staircase structure, wherein the first staircase structure (STd) has a first starting point and a first ending point on a first direction (FD), and wherein the first starting point and the first ending point define a first interval; and a second deck (10-2) adjacent to the first deck along a second direction (VD) perpendicular to the first direction, wherein the second deck comprises a second staircase structure, the second staircase structure has a second starting point and a second ending point on the first direction, and the second starting point and the second ending point define a second interval, and wherein the first interval is adjacent to or has a gap with the second interval; and a memory controller (620, paragraph [0137]) electrically connected to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US Pub. No. 2021/0375918).
Regarding claim 1, in FIG. 5, Zhang discloses a semiconductor device, comprising: a first deck (at least one group of lower peaks and valleys in 100H) comprising a first staircase structure extending along a first direction (X); and a second deck (at least one group of higher peaks and valleys in 100H) adjacent to the first deck along a second direction (Z) perpendicular to the first direction, wherein the second deck comprises a second staircase structure, and wherein the first staircase structure is adjacent to or has a gap with the second staircase structure on the first direction.
Regarding claim 2, in FIG. 5, Zhang discloses that the second deck comprises a stack of conductive layers and isolating layers alternating with each other along the second direction, and the stack of conductive layers and isolating layers is adjacent to the first staircase structure along the second direction (paragraph [0075]).
Regarding claim 3, in FIG. 5, Zhang discloses that the first direction and the second direction define a first plane, wherein a first area is a projection of the first staircase structure on the first plane, wherein a second area is a projection of the second staircase structure on the first plane, and wherein the first area has the same shape as the second area.
Regarding claim 4, in FIG. 5, Zhang discloses that each of the first area and the second area is a V-shaped area.
Regarding claim 5, in FIG. 5, Zhang discloses that the first staircase structure comprises a first staircase substructure and a second staircase substructure, the first staircase substructure comprises first staircase steps descending along the first direction, and the second staircase substructure comprises second staircase steps ascending along the first direction.
Regarding claim 6, in FIG. 5, Zhang discloses that the first deck comprises an array region (adjacent to connection region), a wall region (100F), and a connection region (peak and valley region of 100H) comprising the first staircase structure, wherein the wall region is adjacent to the connection region along a third direction (Y) perpendicular to the first direction and the second direction, and wherein the second staircase steps ascending along the first direction are coupled to the array region via the wall region.
Regarding claim 7, in FIG. 5, Zhang discloses that the first deck comprises a third staircase structure (another lower peak and valley section of 100H), and the third staircase structure is adjacent to the first staircase structure on the first direction, and wherein the second deck comprises a fourth staircase structure (another group of higher peaks and valleys in 100H), and the second staircase structure has a gap with the fourth staircase structure on the first direction.
Regarding claim 8, in FIG. 5, Zhang discloses a third area is a projection of the third staircase structure on the first plane, wherein a fourth area is a projection of the fourth staircase structure on the first plane, and wherein the third area has the same shape as the fourth area.
Regarding claim 9, in FIG. 5, Zhang discloses that each of the first staircase structure and the third staircase structure is in between the second staircase structure and the fourth staircase structure along the first direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sung (US Pub. No. 2022/0189875) in view of Hwang (US Pub. No. 2013/0161821).
Regarding claim 10, in FIG. 2, Sung discloses that the semiconductor device comprises a contact structure having a first segment (CNT2 in STd) in the first deck and a second segment (CNT2 in STc) in the second deck.
Sung appears not to explicitly disclose that each of the first segment and the second segment has a first diameter at the top and a second diameter at the bottom along the second direction, and the first diameter is greater than the second diameter.
The art however well recognized contacts having a first diameter at the top and a second diameter at the bottom along a second direction, and the first diameter is greater than the second diameter to be suitable for use as a contact structure in a memory device. See, for example, Hwang, FIG. 1E, elements 50A-H.
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Sung disclosed contact structure such that each of the first segment and the second segment has a first diameter at the top and a second diameter at the bottom along the second direction, and the first diameter is greater than the second diameter for its recognized suitability as a contact structure in a memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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