DETAILED ACTION
Claims 1-21 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uhrenholt et al. (US2021/0216464).
With respect claim 9, Uhrenholt et al. teaches evict a first cache line from a lower-level cache memory associated with a first central processor unit (CPU) core among a plurality of CPU cores of a processor (see paragraphs 89 and 176; an L1 cache 26 that is associated with the shader cores 25. Also paragraphs 58 and 240-241; when the requested cache line is present in a lower level cache (there is a hit in a lower level cache), then the cache line in question is evicted from the lower level up to the L2 cache), the method comprising:
determining, in the first CPU core, to evict the first cache line from the associated lower-level cache memory among a plurality of lower-level cache memories in a cache memory system (see paragraphs 58 and 240-241; when the requested cache line is present in a lower level cache (there is a hit in a lower level cache), then the cache line in question is evicted from the lower level up to the L2 cache);
identifying a first slice of a plurality of slices of a higher-level cache associated with a target CPU core in which to store the first cache line (see paragraphs 58 and 240-241; in the event that the data is present in the lower level cache, the data is then evicted from the lower level cache to the cache (e.g. the L2 cache) to which the initial read request was made); and
transmitting the first cache line to the target CPU core among the plurality of CPU cores for storage in the first slice (see paragraphs 58 and 240-241; then the cache line in question is evicted from the lower level up to the L2 cache (step 159) (and invalidated in the lower level), and the read request is replayed in the L2 cache).
With respect claim 17, Uhrenholt et al. teaches non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a multi-core processor, cause the multi-core processor to evict a first cache line from a lower-level cache memory associated with a first central processor unit (CPU) core among a plurality of CPU cores of the multi-core processor (see paragraphs 89 and 176; an L1 cache 26 that is associated with the shader cores 25. Also paragraphs 58 and 240-241; when the requested cache line is present in a lower level cache (there is a hit in a lower level cache), then the cache line in question is evicted from the lower level up to the L2 cache), wherein evicting the first cache line comprises:
determine, in the first CPU core, to evict the first cache line from the associated lower-level cache memory among a plurality of lower-level cache memories in a cache memory system (see paragraphs 58 and 240-241; when the requested cache line is present in a lower level cache (there is a hit in a lower level cache), then the cache line in question is evicted from the lower level up to the L2 cache);
identify a first slice of a plurality of slices of a higher-level cache associated with a target CPU core in which to store the first cache line (see paragraphs 58 and 240-241; in the event that the data is present in the lower level cache, the data is then evicted from the lower level cache to the cache (e.g. the L2 cache) to which the initial read request was made); and
transmit a first cache line to the target CPU core among the plurality of CPU cores for storage in the first slice (see paragraphs 58 and 240-241; then the cache line in question is evicted from the lower level up to the L2 cache (step 159) (and invalidated in the lower level), and the read request is replayed in the L2 cache).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt et al. (US2021/0216464) in view of Hum et al. (US2014/0189239).
With respect claim 1, Uhrenholt et al. teaches a cache memory system (see paragraoh 176; cache system) comprising:
a plurality of lower-level cache memories (see paragraph 176; L1 cache); and
a higher-level cache memory comprising a plurality of slices that each provide a portion of the higher-level cache memory (see paragraph 185; the L2 cache 24 is shown as being configured as respective separate physical cache portions (slices)); and
a plurality of central processing unit (CPU) cores (see Figs. 3 and 4 and paragraphs 89 and 185; processing unit and cores 25) each associated with a corresponding one of the plurality of lower-level cache memories (see paragraph 176; an L1 cache 26 that is associated with the shader cores 25) and a corresponding slice of the plurality of slices of the higher-level cache memory (see Figs. 3 and 4; and paragraph 185; cores 25 coupled to L2 cache portions (slices));
wherein a first CPU core of the plurality of CPU cores is configured to: determine to evict a first cache line from the associated lower-level cache memory of the plurality of lower-level cache memories (see paragraphs 58 and 240-241; when the requested cache line is present in a lower level cache (there is a hit in a lower level cache), then the cache line in question is evicted from the lower level up to the L2 cache);
identify a second CPU core of the plurality of CPU cores comprising the associated first slice of the plurality of slices in which to store the first cache line (see paragraphs 58 and 240-241; in the event that the data is present in the lower level cache, the data is then evicted from the lower level cache to the cache (e.g. the L2 cache) to which the initial read request was made); and
transmit the first cache line to the second CPU core for storage in the first slice (see paragraphs 58 and 240-241; then the cache line in question is evicted from the lower level up to the L2 cache (step 159) (and invalidated in the lower level), and the read request is replayed in the L2 cache).
Uhrenholt et al. does not teach a cache manager circuit configured to maintain data coherence in the cache memory system.
However, Hum et al. teaches a cache manager circuit configured to maintain data coherence in the cache memory system (see paragraphs 40-41; cache coherency aware memory controller).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the processor taught by Uhrenholt et al. to include the above mentioned to help improve performance of the device (see Urenholt, paragraph 40).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt et al. (US2021/0216464) and Hum et al. (US2014/0189239) as applied to claim 1 above, and further in view of Knebel (US2009/0106494).
With respect claim 2, Uhrenholt et al. and Hum et al. do not teach wherein to identify the first slice, the first CPU core is further configured to: send a first message to the cache manager circuit indicating eviction of the first cache line; and receive, from the cache manager circuit, a second message comprising an identifier of the second CPU core.
However, Knebel teaches send a first message to the cache manager circuit indicating eviction of the first cache line (see paragraph 24 and 27; when a line is evicted from one of the upper-level L1 caches, that L1 cache sends a hint transaction signal to the L2 cache 118, indicating the address or other information pertaining to the evicted line. In turn, the L2 cache 118 uses the address or other information in the signal to locate the corresponding line in the L2 cache 118 and updates the hint bit 314 associated with that line to reflect that the data is no longer stored in the L1 cache); and receive, from the cache manager circuit, a second message comprising an identifier of the second CPU core (see claim 2; wherein the processor core provides an identification signal to the cache controller, and wherein the cache controller uses said identification signal to determine in which of a plurality of cache ways said space should be allocated).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the processor taught by Uhrenholt et al. and Hum et al. to include the above mentioned to improve performance of the cache memory (see Knebel, paragraph 9).
With respect claim 3, Uhrenholt et al. teaches wherein the first CPU core is further configured to transmit the first cache line directly to the second CPU core on a system interface (see Fig. 2 and paragraph 180; L2 cache 24 also includes an appropriate interconnect 23 for transferring data between the L2 cache 24 and the L1 cache 26 (shader cores 25)).
Claim(s) 10-11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt et al. (US2021/0216464) in view of Knebel (US2009/0106494).
With respect claim 10, Uhrenholt et al. does not teach wherein identifying the first slice further comprises the first CPU core: sending a first message to a cache manager circuit indicating eviction of the first cache line; and receiving, from the cache manager circuit, a second message comprising an identifier of a second CPU core.
However, Knebel teaches sending a first message to the cache manager circuit indicating eviction of the first cache line (see paragraph 24 and 27; when a line is evicted from one of the upper-level L1 caches, that L1 cache sends a hint transaction signal to the L2 cache 118, indicating the address or other information pertaining to the evicted line. In turn, the L2 cache 118 uses the address or other information in the signal to locate the corresponding line in the L2 cache 118 and updates the hint bit 314 associated with that line to reflect that the data is no longer stored in the L1 cache); and receiving, from the cache manager circuit, a second message comprising an identifier of the second CPU core (see claim 2; wherein the processor core provides an identification signal to the cache controller, and wherein the cache controller uses said identification signal to determine in which of a plurality of cache ways said space should be allocated).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Uhrenholt et al. to include the above mentioned to improve performance of the cache memory (see Knebel, paragraph 9).
With respect claim 11, Uhrenholt et al. teaches the first CPU core transmitting the first cache line directly to the second CPU core on a system interface(see Fig. 2 and paragraph 180; L2 cache 24 also includes an appropriate interconnect 23 for transferring data between the L2 cache 24 and the L1 cache 26 (shader cores 25)).
With respect claim 18, Uhrenholt et al. does not teach send a first message to a cache manager circuit indicating eviction of the first cache line; and receive, from the cache manager circuit, a second message comprising an identifier of a second CPU core.
However, Knebel teaches send a first message to the cache manager circuit indicating eviction of the first cache line (see paragraph 24 and 27; when a line is evicted from one of the upper-level L1 caches, that L1 cache sends a hint transaction signal to the L2 cache 118, indicating the address or other information pertaining to the evicted line. In turn, the L2 cache 118 uses the address or other information in the signal to locate the corresponding line in the L2 cache 118 and updates the hint bit 314 associated with that line to reflect that the data is no longer stored in the L1 cache); and receive, from the cache manager circuit, a second message comprising an identifier of the second CPU core (see claim 2; wherein the processor core provides an identification signal to the cache controller, and wherein the cache controller uses said identification signal to determine in which of a plurality of cache ways said space should be allocated).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Uhrenholt et al. and Hum et al. to include the above mentioned to improve performance of the cache memory (see Knebel, paragraph 9).
Allowable Subject Matter
Claims 4-8, 12-16 and 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 01/15/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues, in pages 8-10 and 12, that Urenholt et al. does not teach “determining, in the first CPU core, to evict the first cache line from the associated lower-level cache memory" as cited in claims 1, 9 and 17, because Uhrenholt et al. states that the cited response to the read request, which includes eviction etc., is performed by the "cache and the cache system" and not by the "shader cores 25".
In response: The examiner disagrees. Even though Urenholt et al. does not explicitly teach the shared cores 25 determining data to be evicted, Urenholt et al. teaches a processing unit, where the processing unit is a data encode (see paragraph 89 and 94); the data encoder 22 checks for the presence of the data that it requires in the L2 cache (or lower), for example so as to be able to determine whether it needs to return data to the memory system, without a read to the memory system itself being triggered (and correspondingly avoiding the triggering of any read to the memory system where the data encoder 22 can determine that such a read to the memory system itself is not necessary). This then allows the data encoder 22 to handle and control the eviction of data from the L2 cache to the memory system in a way that, for example, avoids read transactions to the memory system where they are not required (i.e., processing unit determined data to be evicted) (see paragraph 247-248).
Applicant’s representative argues, in page 11, that Knebel et al. does not cure the deficiencies of Urenholt et al. discussed above.
In response: See the above Examiner’s response.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139