Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species II, claims 1-5, 11-21, & 24-25 in the reply filed on June 20th, 2026 is acknowledged. The traversal is on the grounds that due to their similar technical features; it would not be a serious search burden on the examiner. This is not found persuasive because the search area for Species II does not intrinsically cover that of species one, as they have distinct structural differences. For example, Species I has a PNPN diode while Species II has a PN-i-PN diode. Due to this, Species has an extra region, the intrinsically doped region, which changes the structure formed between the two species.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The disclosure is objected to because of the following informalities:
In Paragraph [0027] the P-type intrinsic doped region is incorrectly labeled as NIN multiple times throughout the paragraph. This should be relabeled as NTN, which is what the p-type intrinsic doped region was labeled as in paragraph [0024] and in Fig. 4.
Appropriate correction is required.
Claim Objections
Claim 25 is objected to because of the following informalities:
In claim 25, there are mentions of “the second P-type doped region” and “the first N-type doped region”. It is assumed that these were meant to be “the second P-type heavily doped region” and “the first N-type heavily doped region” respectively since there is no prior mention of these claimed elements in the claims that claim 25 are dependent on (As these were the names given to the limitations in independent claim 1, rather than what is presented in independent claim 19 which claim 25 depends from).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mao et al. (US 20230022588 A1).
Regarding claim 1, Mao et al. teaches an electrostatic discharge protection device (Paragraph 0002), comprising:
A P-type semiconductor substrate (Paragraph 0057 describes a P-type substrate, 1 in Fig. 1);
A p-type well region located in the P-type semiconductor substrate (Paragraph 0058 shows a P-type well, 3, in the P-type substrate. Fig 1);
A deep N-type well region located in the P-type semiconductor substrate and below the P-type well region (Paragraph 0078 has a deep N-type well, 2, formed in the substrate, 1. The P-type well, 3, is formed on top of the deep N-type well. Fig 1);
A first N-type doped region located on the P-type well region (Paragraph 0058 describes a first N-type doped region, 13, formed on the p-well, 3);
A first P-type doped region located on the deep N-well region (Fig 1 shows a P-type doped region, 12, located in the P well, 3, which is directly above the deep N-well region, 2), wherein the first N-type doped region and the first P-type doped region are arranged side-by-side and spaced apart from each other (See arrangement of the N-type doped region, 13, and the P-type doped region, 12, in Fig. 1),
An N-type well region located in the P-type semiconductor substrate (Paragraph 0060 describes a N-type well, 4, being formed);
A second N-type doped region located on the N-type well region (Paragraph 0061 describes a N-type doped region, 15, in the N well, 4. Shown in Fig 1); and
A second P-type doped region located on the N-type well region (Paragraph 0061 describes a p-type doped region, 16, in the N well, 4. Shown in Fig 1), wherein the second N-type doped region and the second P-type doped region are arranged side-by-side and spaced apart from each other (Fig 1 shows the N-type doped region, 15, arranged side-by-side and spaced apart with the p-type doped region, 16),
Wherein the first P-type doped region is electronically connected to the second N-type doped region (Paragraph 0061 describes the p-type doped region, 12, and a n-type doped region, 15, both connected to the diode string, 200).
Regarding claim 2, Mao et al. teaches the first N-type doped region being electrically connected to an input/output terminal (Paragraph 0010 states that the first N-type doped region, 13, is electrically connected to the anode, which has the capacity to be an input/output terminal), and the second P-type doped region being electrically connected to a ground terminal (Paragraph 0061 states that the second p-type doped region, 14, is electrically connected to the cathode, which serves as the grounding terminal).
Regarding claim 3, Mao et al. teaches the first N-type doped region being electrically connected to a power supply terminal (Paragraph 0010 states that the first N-type doped region, 13, is electrically connected to the anode, which has the capability to be a power supply terminal), and the second P-type doped region being electrically connected to an input/output terminal (Paragraph 0061 states that the second p-type doped region, 14, is electrically connected to the cathode, which has the capacity to be an input/output terminal).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al. (US 20230022588 A1) in view of Xu (US 20230012968 A1).
Regarding claim 4, Mao et al. teaches the P-type well region and the first N-type doped region forming a first parasitic diode (Paragraph 0062 describes the first N-type doped region, 13, and the P well, 3, forming the diode, 108), and the second P-type doped region and the N-type well region forming a second parasitic diode (Paragraph 0062 describes the second p-type doped region, 14, and the N well forming the diode, 107).
Mao does not teach the first parasitic diode and the second parasitic diode connected in series by the first P-type doped region and the second N-type doped region.
Xu teaches the first parasitic diode and the second parasitic diode connected in series by the first P-type doped region and the second N-type doped region.
(Figure 3 shows a circuit diagram in which two diodes, D1 and D2, are connected in series. Figure 4 shows the two diodes connected to the p-type and n-type doped regions within two of the wells. Paragraph 0024 states that the third doped well, NW2, may also be a P-type doped well).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mao et al. to have the two parasitic diodes connected in series, as taught by Xu, because having the two diodes in series allows for them to withstand much higher voltages, which increases the protection of the device.
Regarding claim 5, Mao et al., as modified teaches the N-type well region surrounding sidewalls of the P-type well region, and the deep N-type well region is in contact with bottoms of the P-type well region and the N-type well region (Fig 1 shows the N well, 4, in direct contact with the sides of the p well, 2, as long with showing the Deep N well, 2, in direct contact with the bottoms of the two wells).
Claims 19-21, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al. (20230012968 A1) in view of Wang et al. (US 9318481).
Regarding claim 19, Mao et al. teaches an electrostatic discharge protection device (Paragraph 0002), comprising:
A P-type semiconductor substrate (Paragraph 0057 describes a P-type substrate, 1 in Fig. 1);
A P-type well region having a first doping concentration located in the semiconductor substrate (Paragraph 0058 shows a P-type well, 3, in the P-type substrate. Fig 1. As the p-type well region is doped it intrinsically has a doping concentration);
An N-type heavily doped region located on the P-type well region (Paragraph 0058 describes a first N-type doped region, 13, formed on the p-well, 3. Paragraph 0074 describes the first N-type doped region being heavily doped);
A first P-type heavily doped region located on the P-type doped region (Fig 1 shows a P-type doped region, 12, located in the P well, 3. Paragraph 0074 describes the first P-type doped region being heavily doped) wherein the first N-type heavily doped region is arranged side-by-side and spaced apart from each other (See arrangement of the N-type heavily doped region, 13, and the P-type heavily doped region, 12, in Fig. 1);
A deep N-type well region located in the P-type semiconductor substrate and below the P-type well region and the first P-type heavily doped region (Paragraph 0078 has a deep N-type well, 2, formed in the substrate, 1. The P-type well, 3, is formed on top of the deep N-type well. Fig 1).
An N-type well region located in the P-type semiconductor substrate (Paragraph 0060 describes a N-type well being formed);
A second N-type heavily doped region located on the N-type well region (Paragraph 0061 describes a N-type doped region, 15, in the N well, 4. Shown in Fig 1. Paragraph 0074 describes the second N-type doped region being heavily doped); and
A second P-type heavily doped region located on the N-type well region (Paragraph 0061 describes a p-type doped region, 16, in the N well, 4. Shown in Fig 1. Paragraph 0074 describes the second P-type doped region being heavily doped), wherein the second N-type heavily doped region are arranged side-by-side and spaced apart from each other (Fig 1 shows the N-type doped region, 15, arranged side-by-side and spaced apart with the p-type doped region, 16),
Wherein the first P-type heavily doped region is electrically connected to the second N-type heavily doped region (Paragraph 0061 describes the p-type doped region, 12, and a n-type doped region, 15, both connected to the diode string, 200)
Mao et al. does not teach a P-type doped region having a second doping concentration located in the P-type semiconductor substrate, wherein the P-type well region and the P-type doped region are adjacent to each other, the first P-type heavily doped region located on the P-type doped region; and the deep N-type well region located below the P-type doped region.
Wang et al. teaches a P-type doped region having a second doping concentration located in the P-type semiconductor substrate (Fig 3H shows a p-well, 162, above a second p-well, 164, and in a P-type substrate, 152. As the P-well, 162, is doped, it intrinsically has a doping concentration, therefore is a p-type doped region.), wherein the P-type well region and the P-type doped region are adjacent to each other (Fig 3H shows show the p-type doped region, 162, directly below, therefore adjacent to the p-well, 164), the first P-type heavily doped region located on the P-type doped region (The addition of the P-type doped region, 162, from Wang et al. directly below the P-type well, 3, in Mao et al. would have the heavily P-type doped region, 12, from Mao et al. would be on the P-type doped region); and the deep N-type well region located below the P-type doped region (The addition of the P-type doped region, 162, from Wang et al. directly below the P-type well, 3, of Mao et al. by turning the well into two P-type regions 162 and 164, would result in the N-type heavily doped region, 2, from Mao et al., being directly below the P-type doped region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mao et al. to have cut the P-type well vertically in half to create two P-type wells, as taught by Wang et al., because two separate p-wells allows for the structure to be optimized for its own voltage range and current path, which allows for the ESD structure to handle higher voltages and currents.
Regarding claim 20, Mao et al., as modified, teaches the first N-type heavily doped region is electrically connected to an input/output terminal (Paragraph 0010 states that the first N-type doped region, 13, is electrically connected to the anode, which has the capacity to be an input/output terminal), and the second P-type heavily doped heavily doped region is electrically connected to a ground terminal (Paragraph 0061 states that the second p-type doped region, 14, is electrically connected to the cathode, which serves as the grounding terminal).
Regarding claim 21, Mao et al., as modified, teaches the first N-type heavily doped region is electrically connected to a power supply terminal (Paragraph 0010 states that the first N-type doped region, 13, is electrically connected to the anode, which has the capability to be a power supply terminal), and the second P-type heavily doped region is electrically connected to an input/output terminal (Paragraph 0061 states that the second p-type doped region, 14, is electrically connected to the cathode, which has the capacity to be an input/output terminal).
Regarding claim 24, Mao et al., as modified, does not teach the first doping concentration being higher than the second doping concentration, and wherein the second doping concentration is equal to a third doping concentration of the P-type semiconductor substrate.
Wang et al. teaches the first doping concentration being higher than the second doping concentration (Paragraph 21 describes that the P-type well, 164, is more highly doped than the P-type doped region, 162).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mao et al. to have the P-type well have a larger doping concertation than the rest of the substrate, as taught by Wang et al., because higher doping for the p-type well improves current transport efficiency, allowing for the well to better handle electrostatic discharge without overheating or damaging the device.
Further, it would also be obvious to keep the base substrate and the P-type doped region at the same concentration as it would require less steps to keep them the same, making the design of the ESD easier and simple, therefore reading on the limitation of the second doping concentration is equal to a third doping concentration of the P-type semiconductor substrate.
Regarding claim 25, Mao et al. teaches the second P-type doped region, the N-type well region, P-type doped region, the P-type well region, and the first N-type doped region form a parasitic diode (Figs 1 and 2 shows the diodes. Paragraph 0062 explains how the diodes connect to the wells and the doped regions. These diodes connect to create a parasitic PNPN diode).
Mao does not teach the extra intrinsic layer that would make the diode a PN-i-PN diode.
Wang et al. teaches an intrinsic region in between a n-type well and a p-type well to form a parasitic diode (Paragraph 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mao et al. to add an intrinsic region in order to form a parasitic PN-i-PN diode, as taught by Wang et al., because an intrinsic layer allows for better control over the voltage and the current of the ESD, which allows for it to more successfully divert electrostatic discharge without damaging the electronics being protected.
Allowable Subject Matter
Claims 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach or render obvious the first P-type doped region is located directly on a P-type intrinsic doped region surrounded by the N-type well region, the deep N-type well region, and the P-type well.
As there is currently no P-type intrinsic doped region in Mao et al., one would need to be taught in. Adding a P-type intrinsic doped region to would require changing the entire structure of Mao et al. in order to fit the specific location required for claim 11. Therefore, it would not be obvious to one of ordinary skill in the art to teach in the intrinsic layer.
Since claims 12-18 are all dependent on claim 11, they are objected to with the same reasoning.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen (US 12,622,065 B2), Cheng et al. (US 20210249403 A1), and Salcedo et al. (20160300830 A1) share a similar structure in which a n-type deep well is formed on a p-type substrate. A p-type well and n-type well are both formed on top of the deep N-type well. Within these wells are P-type doped regions and N-type doped regions that are placed side by side to each other.
Williams et al. (US 20080237783 A1) has a p-type pocket that works as an intrinsic region. This region has a p-type doping concentration that is smaller from the p-type well. Adjacent to the pocket are a N-type well and a P-type well which contain individual doped regions.
Fan (CN 114429950 A) has a P-type well adjacent to a N-type well, with a P-type epitaxial layer and a deep N-type well between the wells, the epitaxial P-type layer, and the substrate. Both wells containing alternative P-type and N-type doped regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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