DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention 1, claims 1 – 11, in the reply filed on 7/7/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Huang figure 5 and annotated figure 1B
Claims 19 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20240055499 A1), hereinafter referred to as "Huang".
Regarding claim 19, Huang discloses an analog cell structure, comprising: a first feed-through via (202 in Huang figure 5) and a second feed-through via (204 in Huang figure 5) extending in a first direction and separated by a first distance in a second direction perpendicular to the first direction (they extend left-to-right and are separated up-to-down in Huang figure 5); a CMOS structure disposed between the first feed-through via and the second feed- through via and comprising a plurality of polysilicon layers (226 and 228 in Huang figure 5. They are common poly on oxide diffusion edges, where poly is a shortening for polysilicon), a PMOS active region (210 in Huang figure 5), a NMOS active region (214 in Huang figure 5), and a first metal diffusion pattern (220/222/224 in Huang figure 5); a metal routing layer (backside PDN 8 in Huang figure 1B, which comprises 230 and 242 in figure 5); and a plurality of vias (The wiring layer 8 in figure 1B comprises additional vias on the backside, see Huang annotated figure 1B), wherein the first feed-through via, the second feed-through via, and a first via of the plurality of vias are configured to provide backside connection to the CMOS structure (Huang paragraphs 0080-0082).
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Regarding claim 21, Huang discloses a circuit device (200 in Huang figure 5), comprising: a substrate (245 in figure 6) having a first surface (between epi/MD and 245 in figure 6) and a second surface opposite to the first surface (between 245 and BM0 in figure 6); a cell disposed on the first surface of the substrate (206 and 208 in figure 5), the cell comprising an n-type metal oxide semiconductor (NMOS) active region (214 in figure 5) and a p-type metal oxide semiconductor (PMOS) active region (210 in figure 5) both extending in a first direction (they extend left-to-right in figure 5); a first via disposed in the substrate extended between the first surface and the second surface (power via 204 in figure 5 and 6); and a second via disposed under the NMOS active region or the PMOS active region and extended to the second surface of the substrate (this structure can be repeated, see figure 1B, and so another via similar to 204 would be present, which would be both under the NMOS and PMOs active regions and extend to the second surface, see figure 6).
Regarding claim 22, Huang discloses all of the limitations of claim 21. Huang further discloses that the first via is a first feed-through via disposed on a same side of the NMOS active region and the PMOS active region (204 is on the same side of the NMOS and PMOS active regions, below in figure 5) extending in the first direction (It extends left-to-right).
Regarding claim 23, Huang discloses all of the limitations of claim 22. Huang further discloses a second feed-through via (202 in figure 5) disposed on the other side of the NMOS active region and the PMOS active region (it is above the NMOS and PMOS active regions in figure 5).
Regarding claim 24, Huang discloses all of the limitations of claim 21. Huang further discloses a metal routing structure (242 and 230 in figure 5) disposed on the second surface of the substrate (see 242 in figure 6) and coupled to the cell through the first via and the second via (see power via in figure 6).
Regarding claim 25, Huang discloses all of the limitations of claim 21. Huang further discloses that the cell comprises a plurality of polysilicon segments (226 and 228 in figure 5), and a plurality of metal diffusion segments (220, 222, and 224 in figure 5) extending in a second direction perpendicular to the first direction (they extend up-to-down in figure 5, which is perpendicular to the left-to-right first direction), wherein the NMOS active region, PMOS active region, plurality of polysilicon segments, and plurality of metal diffusion segments make up a CMOS structure (the active regions in figure 5 are linked up like a CMOS structure, and Huang teaches the device can perform the function of an inverter, like CMOS can be used for; see Huang paragraph 0078 and 0079).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Claims 1-3, 5-7, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chou et al. (US 20190179993 A1), hereinafter referred to as "Chou".
Regarding claim 1, Huang discloses an analog circuit device, comprising: a metal routing layer comprising a plurality of tracks (backside PDN 8 in Huang figure 1B, which comprises 230 and 242 in figure 5); an analog cell comprising an n-type metal oxide semiconductor (NMOS) active region (214 in Huang figure 5) and a p-type metal oxide semiconductor (PMOS) active region (210 in Huang figure 5), a plurality of polysilicon layers (226 and 228 in Huang figure 5. They are common poly on oxide diffusion edges, where poly is a shortening for polysilicon), and a plurality of metal diffusion layers (220, 222, and 224 in Huang figure 5), wherein the NMOS active region, PMOS active region, plurality of polysilicon layers, and plurality of metal diffusion layers make up a CMOS structure (the active regions in figure 5 are linked up like a CMOS structure, and Huang teaches the device can perform the function of an inverter, like CMOS can be used for; see Huang paragraph 0078 and 0079); and a power rail structure (202 and 204 in Huang figure 5) configured to provide backside routing to the analog cell by providing a connection between the metal routing layer and the analog cell (Huang paragraphs 0080-0082).
Huang does not disclose a plurality of guard ring cells surrounding the analog cell.
Chou teaches an analog circuit device with a plurality of guard ring cells surrounding the analog cell (Chou figure 4; each Active Cell Structure is surrounded by guard rings). Chou also teaches that the guard ring cells can reduce leakage current and isolate the associated active cell structures from noise (Chou paragraph 0029).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the guard ring cells surrounding the analog cell, as in Chou, in order to reduce leakage current and isolate the associated active cell structures from noise.
Regarding claim 2, Huang in view of Chou discloses all of the limitations of claim 1. Huang further discloses that the power rail structure comprises at least one feed-through via (202 and 204 are vias that feed through the substrate, see Huang figure 6) and at least one backside via (The wiring layer in figure 1B comprises additional vias on the backside, see Huang annotated figure 1B).
Regarding claim 3, Huang in view of Chou discloses all of the limitations of claim 2. Huang further discloses that the at least one feed-through via comprises a first feed-through via (202 in Huang figure 5) and a second feed-through via (204 in Huang figure 5) extending in a first direction and separated in a second direction (they extend left-to-right and are separated up-to-down in Huang figure 5), and wherein the analog cell is disposed between the first feed-through via and the second feed-through via (the parts of the cell containing the N and P type regions and the polysilicon lines are between the feed-through vias).
Regarding claim 5, Huang in view of Chou discloses all of the limitations of claim 1. Chou further discloses that the analog cell comprises one of a plurality of analog cells (Active Cell Structures 1-4 in Chou figure 4); the plurality of analog cells and the plurality of guard ring cells are arranged in an array comprising rows and columns (Chou figure 4); and the cells are arranged such that each analog cell of the plurality of analog cells is surrounded by guard ring cells of the plurality of guard ring cells (Chou figure 4; each active cell structure is surrounded by guard rings H, V, C, and I).
Regarding claim 6, Huang in view of Chou discloses all of the limitations of claim 5. Chou further discloses that the plurality of guard ring cells comprises an outer border of guard ring cells comprising: four corner guard ring cells (Guard Ring C in Chou figure 4); at least one horizontal guard ring cell (Guard Ring H in Chou figure 4); and at least one vertical guard ring cell (Guard Ring V in Chou figure 4), wherein a first corner guard ring cell of the four corner guard ring cells comprises a first guard ring structure (Chou paragraph 0029); the at least one vertical guard ring cell is adjacent to the first corner guard ring cell (Guard Ring V_2 is adjacent to Guard Ring C_2 in Chou figure 4) and comprises a second guard ring structure (Chou paragraph 0029); and wherein the first guard ring structure interfaces with the second guard ring structure (the cells directly contacting each other in figure 4 will create some sort of interface).
Regarding claim 7, Huang in view of Chou discloses all of the limitations of claim 6. Chou further discloses a third guard ring structure within a second corner guard ring cell (Guard Ring C_3 in Chou figure 4, which also has a guard ring structure), wherein the at least one vertical guard ring cell is disposed between the first corner guard ring cell and the second corner guard ring cell (Guard ring V_2 is between Guard Ring C_2 and Guard Ring C_3).
Regarding claim 9, Huang in view of Chou discloses all of the limitations of claim 1. Chou further discloses that a first guard ring cell of the plurality of guard ring cells comprises a guard ring structure and the guard ring structure comprises a dummy structure (Chou paragraph 0029).
Regarding claim 11, Huang in view of Chou discloses all of the limitations of claim 1. Huang further discloses that the power rail structure comprises a feed- through via (204 in Huang figure 5) disposed between a first track of the plurality of tracks and a portion of a first metal diffusion layer of the plurality of the metal diffusion layers (see Huang figure 6; 204 is between metal track 242 and metal diffusion layer 224) and a backside via (The wiring layer in figure 1B comprises additional vias on the backside, see Huang annotated figure 1B) disposed between a second track of the plurality of tracks and one of the PMOS active region and the NMOS active region (The additional vias are above other metal lines and below the feedthrough vias and thus also below the PMOS and NMOS active regions).
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chou as applied to claim 3 above, and further in view of Peng et al. (US 20210343645 A1), hereinafter referred to as "Peng".
Regarding claim 4, Huang in view of Chou discloses all of the limitations of claim 3.
Huang does not explicitly disclose that one of the polysilicon layers is tied off in a first and second break region.
Peng teaches a cell with at least one polysilicon layer tied off (which is taken here to mean that the line ends at and is connected to) in a first break region and a second break region in a first and second via (Peng figure 43A, the gates 130, which are commonly made of polysilicon, end at the backside vias 115 on either end. The vias are between the gates and the metal lines, and the region where it contacts the gate can be considered the break region). Peng also teaches that this device improves device performance and provides routing flexibility.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the polysilicon layers tied off like the gates in Peng in order to improve device performance and provide routing flexibility.
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Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chou as applied to claim 1 above, and further in view of Chen et al. (US 20210375853 A1), hereinafter referred to as "Chen".
Regarding claim 8, Huang in view of Chou discloses all of the limitations of claim 1. Huang does not explicitly disclose that the NMOS and PMOS active regions extend outside of the cell boundary.
Chen teaches analog cell structures with NMOS and PMOS active regions (OD1 and OD2 in Chen figure 3) that extend outside of the cell boundary (302 in Chen figure 3 is a standard cell, see Chen paragraph 0065, which OD1 extends beyond the outside boundary of. The structure is mirrored on the other side, where OD2 has an opposite conductivity to OD1, see Chen paragraph 0061). Chen also teaches that this can be used for more than one circuit device by being elongated in this direction (Chen paragraph 0021).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the NMOS and PMOS active regions extend beyond the outside of the cell boundary, like in Chen in order to use the same active region for multiple devices, which could simplify manufacturing.
Regarding claim 10, Huang in view of Chou discloses all of the limitations of claim 1. Chou further discloses that a first guard ring cell of the plurality of guard ring cells comprises a guard ring structure (Chou paragraph 0029).
Chou does not explicitly disclose that the guard ring structure comprises an oxide structure.
Chen teaches a guard ring structure (Chen paragraph 0022, the structure 100A can be a dummy transistor, which can act as a guard ring) where the guard ring structure comprises an oxide structure (Chen paragraph 0022; the dummy gate P1 is a continuous-poly-on-oxide-definition edge region and thus has an oxide structure). Chen also teaches that this can reduce parasitic capacitances (Chen paragraph 0019).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the oxide structure of Chen in order to reduce parasitic capacitances.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 19 above, and further in view of Chou.
Regarding claim 20, Huang discloses all of the limitations of claim 19. Huang does not explicitly disclose a guard ring structure.
Chou teaches an analog cell structure that is disposed adjacent to a guard ring cell comprising a guard ring structure (Chou figure 4; each Active Cell Structure is surrounded by guard rings). Chou also teaches that the guard ring cells can reduce leakage current and isolate the associated active cell structures from noise (Chou paragraph 0029).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the guard ring cells adjacent to the analog cell, as in Chou, in order to reduce leakage current and isolate the associated active cell structures from noise.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 21 above, and further in view of Chou.
Regarding claim 26, Huang discloses all of the limitations of claim 21. Huang does not explicitly disclose a guard ring structure.
Chou teaches a guard ring cell disposed adjacent to the cell (Chou figure 4; each Active Cell Structure is surrounded by guard ring cells). Chou also teaches that the guard ring cells can reduce leakage current and isolate the associated active cell structures from noise (Chou paragraph 0029).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the guard ring cells adjacent to the analog cell, as in Chou, in order to reduce leakage current and isolate the associated active cell structures from noise.
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Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen as applied to claim 26 above, and further in view of Chen.
Regarding claim 27, Huang in view of Chou discloses all of the limitations of claim 26. Chou further discloses that the guard ring cell comprises a guard ring structure (Chou paragraph 0029), and the guard ring structure is disposed on an opposite side of which the guard ring cell is adjacent to the cell (the guard ring structures are disposed an all sides of the analog cells in Chou figure 4).
Neither Huang nor Chou disclose that the guard ring structure is disposed on a polysilicon layer.
Chen discloses a guard ring structure (Chen paragraph 0022, the structure 100A can be a dummy transistor, which can act as a guard ring) disposed on a polysilicon layer (See Chen figure 1B; 151 can be polysilicon, see Chen paragraph 0037). Chen also teaches that this structure can reduce parasitic capacitances and achieve improved unit gain frequency (Chen paragraph 0019).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the oxide structure of Chen in order to reduce parasitic capacitances and achieve improved unit gain frequency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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