DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on January 14, 2026.
Claims 1, 9, and 17 are amended. No claims are canceled. No claims are added.
Response to Arguments
3. Applicant's arguments filed January 14, 2026 have been fully considered but they are not persuasive.
Applicant asserts on page 10 that Guo (US 20230343400 A1) never teaches, suggests, or enables "independently erasable" lateral sub-blocks and that Guo's lateral "fingers" (regions 420, 430, 440, 450) are portions of a word line layer divided by isolation areas, but the lateral division is not disclosed as an independently erasable unit.
However, Guo teaches in ¶ [0073]:
“The block depicted in FIG. 4B includes a set of isolation areas 402, 404, 406, 408 and 410 that serve to divide each layer of the block into four regions; for example, the top layer depicted in FIG. 4B is divided into regions 420, 430, 440 and 450, which are referred to as fingers. In the layers of the block that implement memory cells, the four regions are referred to as word line fingers that are separated by the isolation areas (also serving as local interconnects). In one embodiment, the word line fingers on a common level of a block connect together at the end of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line only connects to one vertical column in each of regions 420, 430, 440 and 450. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block. In one embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together); therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).”
Referencing Guo FIG. 4B, which is provided in Figure A for convenience, an example “all of four rows connected to a common bit line” mentioned in Guo ¶ [0073] may include vertical columns 422, 432, 442, and 452 connected to bit line 414. Each of vertical column 422, 432, 442, and 452 is in a different stack of fingers (i.e., a different lateral sub-block). Here, “the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).” Therefore, cells in one lateral sub-block (e.g., FIG. 4B, including string 482) may be erased without erasing the cells in other lateral sub-blocks (e.g., FIG. 4B, including strings 484, 486, 488).
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Figure A: FIG. 4B of Guo.
Guo also teaches in ¶ [0073] and ¶ [0081] another embodiment in which word line fingers on the same level are not connected together, allowing each word line finger to operate as a separate word line (¶ [0081]). That is, referencing Guo FIG. 4D (see Figure B, which follows), the word lines of each of fingers 460, 462, 464, and 466 are distinct from one another. Likewise, Guo FIG. 4F (see Figure B) teaches the drain and source select gates may be controlled on a “per-finger” basis (see also ¶ [0082]). This means each stack of fingers (lateral sub-block) may be operated isolated from one another.
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Figure B: FIGS. 4D and 4F of Guo.
Therefore, Guo teaches embodiments in which “lateral sub-blocks” may be independently erased and Applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-2, 9-10, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Guo, et al (US 20230343400 A1), hereinafter Guo, in view of Dong, et al (US 20080137425 A1), hereinafter Dong.
Regarding independent claim 1, Guo teaches a method of performing a programming operation (e.g., FIGS. 7A-B, 16) in a memory device (FIG. 1, 100), comprising the steps of:
preparing a memory block (FIG. 4A, Blocks 0..M-1 of planes 302 and 304) that includes an array of memory cells that are arranged in a plurality of word lines (FIG. 4F, memory cells coupled to WL0..WL47);
with the memory block operating in a lateral sub-block mode (FIG. 4B, sub-blocks 420..450 arranged laterally) in which the memory block is divided into sub-blocks that are independently erasable such that one sub-block can be erased while another sub-block remains programmed (¶ [0073] teaches “the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase),” the “four” referring to rows of vertical columns comprising NAND strings (¶ [0077]), each of which are in a different stack of fingers (FIGS. 4B, 4D, 4F));
ramping down a selected word line (FIG. 14, MWLn; ¶ [0122]) being programmed from a reference voltage (FIG. 14, VCG_RV; ¶ [0122]);
after beginning to ramp down the selected word line from the reference voltage, sequentially ramping down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block (FIG. 14 illustrates unselected word lines closer to the selected word line (e.g., MWLn+1) being ramped down earlier than unselected word lines farther from the selected word line (e.g., MWLn+3), the ramping down of each occurring sequentially and the “ends” being the farthest word lines in each direction from the selected word line (¶ [0125]));
Guo does not teach after the unselected word lines have been sequentially ramped down, ramping up a plurality of unselected word lines that are distant from the selected word line; and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramping up the selected word line to a programming voltage.
Dong teaches after the unselected word lines have been sequentially ramped down (both the instant application (FIG. 12, ¶ [0042]) and Guo (Abstract) describe the “ramping down” as part of the program-verify portion of a program operation preceding the next program pulse (instant application FIG. 12; Guo, FIG. 7C). The program-verify operation aligns with Dong FIG. 10, step 1030, which precedes the next program pulse of FIG. 10, 1020, as illustrated in FIG. 9. Therefore, Dong’s ramping up in FIG. 9 occurs after the unselected word lines have ramped down.), ramping up a plurality of unselected word lines that are distant from the selected word line (Instant application ¶ [0058] and ¶ [0112] define “distant” as at least four word lines away from the selected word line (WLn+4 and farther, WLn-4 and farther); Dong teaches in FIG. 9 unselected word lines WLn+4 and farther (included in waveform 920) and WLn-4 and farther (included in waveform 960) begin ramping at times t2 (waveform 920) and t1 (waveform 960)); and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramping up the selected word line to a programming voltage (Dong FIG. 9 shows selected word line WLn ramping to VPGM1 beginning at t3 and to VPGM2 beginning at t4, both of which are after unselected word lines have begun to ramp up).
Regarding independent claim 9, Guo teaches a memory device (FIG. 1, 100) for performing a programming operation (e.g., FIGS. 7A-B, 16), comprising:
a memory block (FIG. 4A, Blocks 0..M-1 of planes 302 and 304) that includes an array of memory cells that are arranged in a plurality of word lines (FIG. 4F, memory cells coupled to WL0..WL47), the array being divided into at least two laterally divided sub-blocks (FIG. 4B, sub-blocks 420..450 arranged laterally) that are independently erasable such that one sub-block can be erased while another sub-block remains programmed (¶ [0073] teaches “the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase),” the “four” referring to rows of vertical columns comprising NAND strings (¶ [0077]), each of which are in a different stack of fingers (FIGS. 4B, 4D, 4F));
control circuitry (FIG. 1, 110) that is configured to program the memory cells (¶ [0044]) of one of the sub-blocks (¶ [0081], FIG. 4D; conductive layers are broken up by isolation regions, constraining programming to one of the sub-blocks) in a plurality of program loops (¶ [0126]; FIG. 7C), during at least one of the program loops (¶ [0126]) the control circuitry being configured to;
ramp down a selected word line being programmed from a reference voltage (FIG. 14, MWLn; ¶ [0122]);
after beginning to ramp down the selected word line from the reference voltage, sequentially ramp down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block (FIG. 14 illustrates unselected word lines closer to the selected word line (e.g., MWLn+1) being ramped down earlier than unselected word lines farther from the selected word line (e.g., MWLn+3), the ramping down of each occurring sequentially and the “ends” being the farthest word lines in each direction from the selected word line (¶ [0125]));
Guo does not teach after the unselected word lines have been sequentially ramped down, ramp up a plurality of unselected word lines that are distant from the selected word line; and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage.
Dong teaches after the unselected word lines have been sequentially ramped down (both the instant application (FIG. 12, ¶ [0042]) and Guo (Abstract) describe the “ramping down” as part of the program-verify portion of a program operation preceding the next program pulse (instant application FIG. 12; Guo, FIG. 7C). The program-verify operation aligns with Dong FIG. 10, step 1030, which precedes the next program pulse of FIG. 10, 1020, as illustrated in FIG. 9. Therefore, Dong’s ramping up in FIG. 9 occurs after the unselected word lines have ramped down.), ramp up a plurality of unselected word lines that are distant from the selected word line (Instant application ¶ [0058] and ¶ [0112] define “distant” as at least four word lines away from the selected word line (WLn+4 and farther, WLn-4 and farther); Dong teaches in FIG. 9 unselected word lines WLn+4 and farther (included in waveform 920) and WLn-4 and farther (included in waveform 960) begin ramping at times t2 (waveform 920) and t1 (waveform 960)); and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage (Dong FIG. 9 shows selected word line WLn ramping to VPGM1 beginning at t3 and to VPGM2 beginning at t4, both of which are after unselected word lines have begun to ramp up).
Regarding independent claim 17, Guo teaches an apparatus for performing a programming operation in a memory device (Abstract), comprising:
a memory block (FIG. 4A, Blocks 0..M-1 of planes 302 and 304) that includes an array of memory cells that are arranged in a plurality of word lines (FIG. 4F, memory cells coupled to WL0..WL47), the array being divided into at least two laterally divided sub-blocks (FIG. 4B, sub-blocks 420..450 arranged laterally) that are independently erasable such that one sub-block can be erased while another sub-block remains programmed (¶ [0073] teaches “the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase),” the “four” referring to rows of vertical columns comprising NAND strings (¶ [0077]), each of which are in a different stack of fingers (FIGS. 4B, 4D, 4F));
a programming means (FIG. 1, 110; ¶ [0007]) for programming the memory cells (¶ [0044]) of one of the sub-blocks (¶ [0081], FIG. 4D; conductive layers are broken up by isolation regions, constraining programming to one of the sub-blocks) in a plurality of program loops (¶ [0126]; FIG. 7C), during at least one of the program loops (¶ [0126]) the programming means being configured to;
ramp down a selected word line (FIG. 14, MWLn; ¶ [0122]) being programmed from a reference voltage (FIG. 14, VCG_RV; ¶ [0122]),
after beginning to ramp down the selected word line from the reference voltage, sequentially ramp down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block (FIG. 14 illustrates unselected word lines closer to the selected word line (e.g., MWLn+1) being ramped down earlier than unselected word lines farther from the selected word line (e.g., MWLn+3), the ramping down of each occurring sequentially and the “ends” being the farthest word lines in each direction from the selected word line (¶ [0125])).
Guo does not teach after the unselected word lines have been sequentially ramped down, ramp up a plurality of unselected word lines that are distant from the selected word line, and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage.
Dong teaches after the unselected word lines have been sequentially ramped down (both the instant application (FIG. 12, ¶ [0042]) and Guo (Abstract) describe the “ramping down” as part of the program-verify portion of a program operation preceding the next program pulse (instant application FIG. 12; Guo, FIG. 7C). The program-verify operation aligns with Dong FIG. 10, step 1030, which precedes the next program pulse of FIG. 10, 1020, as illustrated in FIG. 9. Therefore, Dong’s ramping up in FIG. 9 occurs after the unselected word lines have ramped down.), ramp up a plurality of unselected word lines that are distant from the selected word line (Instant application ¶ [0058] and ¶ [0112] define “distant” as at least four word lines away from the selected word line (WLn+4 and farther, WLn-4 and farther); Dong teaches in FIG. 9 unselected word lines WLn+4 and farther (included in waveform 920) and WLn-4 and farther (included in waveform 960) begin ramping at times t2 (waveform 920) and t1 (waveform 960)), and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage (Dong FIG. 9 shows selected word line WLn ramping to VPGM1 beginning at t3 and to VPGM2 beginning at t4, both of which are after unselected word lines have begun to ramp up).
Regarding claims 1, 9, and 17, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dong into the method of Guo to include sequentially ramping up source-side and drain-side unselected word lines prior to ramping up the selected word line to a program voltage. The ordinary artisan would have been motivated to modify Guo in the above manner for the purpose of correcting insufficient boosting and reducing program disturb (Dong, ¶ [0055-0059]).
Regarding claim 2, Guo as modified by Dong teaches the limitations of claim 1.
Guo further teaches (¶ [0122], referencing FIGS. 14 and 15) the step of sequentially ramping down the plurality of unselected word lines begins with only ramping down at least two word lines that are nearest the selected word line (MWLn-MWLn-1 and MWLn+1) and then only ramping down at least two next closest word lines (LWLT and MWLn+2) and continues until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages (¶ [0125]).
Regarding claim 10, Guo as modified by Dong teaches the limitations of claim 9.
Guo further teaches sequentially ramping down the plurality of unselected word lines (FIG. 14 illustrates unselected word lines closer to the selected word line (e.g., MWLn+1) being ramped down earlier than unselected word lines farther from the selected word line (e.g., MWLn+3)), the control circuitry is configured to initially only ramp down at least two word lines that are nearest the selected word line (FIG. 14, MWLn-MWLn-1 and MWLn+1; ¶ [0122]), and then only ramp down at least two next closest word lines (FIG. 14, LWLT and MWLn+2; ¶ [0122]) and continue to ramp down the unselected word lines until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages (¶ [0125]).
Regarding claim 18, Guo as modified by Dong teaches the limitations of claim 17.
Guo further teaches when sequentially ramping down the plurality of unselected word lines (¶ [0122], referencing FIGS. 14 and 15), the programming means is configured to initially only ramp down at least two word lines that are nearest the selected word line (MWLn-MWLn-1 and MWLn+1) and then only ramp down at least two next closest word lines (LWLT and MWLn+2) and continue to ramp down the unselected word lines until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages (¶ [0125]).
8. Claims 3-4, 11-12, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guo, et al (US 20230343400 A1), hereinafter Guo, in view of Dong, et al (US 20080137425 A1), hereinafter Dong, and further in view of Dong, et al (US 9620233 B1), hereinafter Dong ‘233.
Regarding claim 3, Guo as modified by Dong teaches the limitations of claim 2.
Guo further teaches the step of sequentially ramping down the plurality of unselected word lines includes a first stage (FIG. 15, e.g., the figure second from the left in which the word lines immediately adjacent to the selected word line are ramped down from VREAD to 0a.u.) and a second stage (FIG. 15, e.g., the figure third from the left and second from the right),
wherein during the first stage, a first number (two, although ¶ [0122] teaches the number may be different) of unselected word lines simultaneously begin to ramp down (e.g., ¶ [0122] teaches MWLn-MWLn-1 and MWLn+1 ramp together),
wherein during the second stage, a second number of unselected word lines simultaneously begin to ramp down (two, although ¶ [0122] teaches the number may be different and MWLn+2 and LWLT ramp together).
Guo does not explicitly teach the second number of unselected word lines is greater than the first number of unselected word lines.
Dong ‘233 teaches the second number of unselected word lines (FIG. 12, Clusters 1 and 2) is greater than the first number (FIG. 12, Cluster 0) of unselected word lines (see also Col. 20, ll. 18-30).
Regarding claim 11, Guo as modified by Dong teaches the limitations of claim 10.
Guo further teaches the control circuitry is configured to sequentially ramp down the plurality of unselected word lines in a first stage (FIG. 15, e.g., the figure second from the left in which the word lines immediately adjacent to the selected word line are ramped down from VREAD to 0a.u.) and a second stage (FIG. 15, e.g., the figure third from the left and second from the right),
wherein during the first stage, the control circuitry simultaneously begins to ramp down a first number of unselected word lines (two, although ¶ [0122] teaches the number may be different and MWLn-MWLn-1 and MWLn+1 ramp together),
wherein during the second stage, the control circuitry simultaneously begins to ramp down a second number of unselected word lines (two, although ¶ [0122] teaches the number may be different and MWLn+2 and LWLT ramp together).
Guo does not explicitly teach the second number of unselected word lines is greater than the first number of unselected word lines.
Dong ‘233 teaches the second number of unselected word lines (FIG. 12, Clusters 1 and 2) is greater than the first number (FIG. 12, Cluster 0) of unselected word lines (see also Col. 20, ll. 18-30).
Regarding claim 19, Guo as modified by Dong teaches the limitations of claim 18.
Guo further teaches the programming means is configured to sequentially ramp down the plurality of unselected word lines in a first stage (FIG. 15, e.g., the figure second from the left in which the word lines immediately adjacent to the selected word line are ramped down from VREAD to 0a.u.) and a second stage (FIG. 15, e.g., the figure third from the left and second from the right),
wherein during the first stage, the programming means simultaneously begins to ramp down a first number (two, although ¶ [0122] teaches the number may be different and MWLn-MWLn-1 and MWLn+1 ramp together) of unselected word lines,
wherein during the second stage, the programming means simultaneously begins to ramp down a second number of unselected word lines (two, although ¶ [0122] teaches the number may be different and MWLn+2 and LWLT ramp together).
Guo does not explicitly teach the second number of unselected word lines is greater than the first number of unselected word lines.
Dong ‘233 teaches the second number of unselected word lines (FIG. 12, Clusters 1 and 2) is greater than the first number (FIG. 12, Cluster 0) of unselected word lines (see also Col. 20, ll. 18-30).
Regarding claims 3, 11, and 19, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dong ‘233 into the method of Guo to include clustering word lines as part of the discharging (ramping down) process (Dong ‘233, FIGS. 11-13). The ordinary artisan would have been motivated to modify Guo in the above manner for the purpose of increasing the size of clusters for increased efficiency or decreasing the size of clusters for increased accuracy (Dong ‘233, Col. 23, ll. 12-22).
Regarding claim 4, Guo as modified by Dong and Dong ‘233 teaches the limitations of claim 3.
Regarding claim 12, Guo as modified by Dong and Dong ‘233 teaches the limitations of claim 11.
Regarding claim 20, Guo as modified by Dong and Dong ‘233 teaches the limitations of claim 19.
Regarding claims 4, 12, and 20, Guo shows in FIGS. 14 and 15 and ¶ [0122] the “first number” of unselected word lines ramping is two, which is no more than four, but fails to show the range of the “first number” of unselected word lines of the claimed limitation. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A).
9. Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Guo, et al (US 20230343400 A1), hereinafter Guo, in view of Dong, et al (US 20080137425 A1), hereinafter Dong, and further in view of Lee, et al (US 20220336025 A1), hereinafter Lee.
Regarding claim 8, Guo as modified by Dong teaches the limitations of claim 1.
Guo does not teach after the step of ramping up the selected word line to the programming voltage, the method further includes the step of ramping up a plurality of remaining unselected word lines to pass voltages.
Lee teaches after the step of ramping up the selected word line to the programming voltage, the method further includes the step of ramping up a plurality of remaining unselected word lines to pass voltages (FIG. 11 as applied to the embodiment of FIGS. 14-15 ramps up “Group 2” (word lines adjacent to the selected WL) after the selected word line has ramped up to VPGM; Guo as modified by Dong and Lee would move Dong’s WLn +1 and WLn-1 from waveforms 920 and 960, respectively (Dong FIG. 11), to Lee’s “Group 2” waveform (Lee FIG. 11)).
Regarding claim 16, Guo as modified by Dong teaches the limitations of claim 9.
Guo does not teach after ramping up the selected word line to the programming voltage, the control circuitry is further configured to ramp up a plurality of remaining unselected word lines to pass voltages.
Lee teaches after ramping up the selected word line to the programming voltage, the control circuitry is further configured to ramp up a plurality of remaining unselected word lines to pass voltages (FIG. 11 as applied to the embodiment of FIGS. 14-15 ramps up “Group 2” (word lines adjacent to the selected WL) after the selected word line has ramped up to VPGM; Guo as modified by Dong and Lee would move Dong’s WLn +1 and WLn-1 from waveforms 920 and 960, respectively (Dong FIG. 11), to Lee’s “Group 2” waveform (Lee FIG. 11)).
Regarding claims 8 and 16, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Guo to include ramping up the word lines adjacent to the selected word line to a pass voltage after the selected word line has ramped up to the program voltage. The ordinary artisan would have been motivated to modify Guo in the above manner for the purpose of preventing electron injection from the WL(i+1) region adjacent to the selected word line WLi to the WL(i−1) region (Lee ¶ [0124]).
10. Claims 5-7 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Guo, et al (US 20230343400 A1), hereinafter Guo, in view of Dong, et al (US 20080137425 A1), hereinafter Dong, and further in view of Chen, et al (US 20190147955 A1), hereinafter Chen.
Regarding claim 5, Guo as modified by Dong teaches the limitations of claim 1.
Guo does not teach the step of ramping down the selected word line from the reference voltage includes ramping the selected word line down to a negative voltage.
Chen teaches the step of ramping down the selected word line from the reference voltage (FIG. 9C, VrA..VrG) includes ramping the selected word line down to a negative voltage (FIG. 16A, word line voltage of “first group” 1401, which includes selected word line WLn (see ¶ [0098] and [0148]), is -3V during pre-charge).
Regarding claim 13, Guo as modified by Dong teaches the limitations of claim 9.
Guo does not teach the control circuitry is configured to ramp down the selected word line from the reference voltage to a negative voltage.
Chen teaches the control circuitry is configured to ramp down the selected word line from the reference voltage (FIG. 9C, VrA..VrG) to a negative voltage (FIG. 16A, word line voltage of “first group” 1401, which includes selected word line WLn (see ¶ [0098] and [0148]), is -3V during pre-charge).
Regarding claims 5 and 13, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Chen into the method of Guo to include a negative word line voltage for the selected word line during pre-charge. The ordinary artisan would have been motivated to modify Guo in the above manner for the purpose of reducing the disturb without the time penalty of a stepped increase (Chen ¶ [0208-0209]).
Regarding claim 6, Guo as modified by Dong and Chen teaches the limitations of claim 5.
Guo further teaches the step of sequentially ramping down the plurality of unselected word lines from the pass voltages includes ramping the unselected word lines down to approximately zero Volts (FIG. 15 and ¶ [0122], in which 0 a.u. (assumed “arbitrary units”) is understood to represent 0V).
Regarding claim 7, Guo as modified by Dong and Chen teaches the limitations of claim 5.
Chen further teaches after the step of ramping up the plurality of unselected word lines that are distant from the selected word line and prior to the step of ramping up the selected word line to the programming voltage, the method further includes the step of ramping up the selected word line from the negative voltage to a positive voltage that is less than the programming voltage (FIG. 16A, -3V pre-charge voltage on the selected word line shown in voltage profile 1610 ramps up to positive voltage 2V shown in voltage profile 1611 (¶ [0210]; see also FIG. 12B and FIG. 10A, step 1003a)).
Regarding claim 14, Guo as modified by Dong and Chen teaches the limitations of claim 13.
Guo further teaches the circuitry is configured to sequentially ramp down the plurality of unselected word lines from the pass voltages to approximately zero Volts (FIG. 15 and ¶ [0122], in which 0 a.u. (assumed “arbitrary units”) is understood to represent 0V).
Regarding claim 15, Guo as modified by Dong and Chen teaches the limitations of claim 13.
Chen further teaches after ramping up the plurality of unselected word lines that are distant from the selected word line and prior to ramping up the selected word line to the programming voltage, the control circuitry is further configured to ramp up the selected word line from the negative voltage to a positive voltage that is less than the programming voltage (FIG. 16A, -3V pre-charge voltage on the selected word line shown in voltage profile 1610 ramps up to positive voltage 2V shown in voltage profile 1611 (¶ [0210]; see also FIG. 12B and FIG. 10A, step 1003a)).
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Maeda (US 20120134210 A1) teaches erasing a first sub-block while not erasing a second sub-block (Abstract), the sub-blocks arranged laterally (e.g., SB1 and SB2 of FIGS. 1 and 3A).
Feeley, et al (US 20140036590 A1) teaches in FIG. 14 laterally arranged “tiles” in which one tile is erased while the adjacent tiles are inhibited from erasing.
Yang, et al (US 20220383956 A1) teaches laterally-arranged sub-blocks (FIGS. 4B, 4E) can be the unit of erase (¶ [0071]), each sub-block independently selectable (¶ [0087]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827