Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “one or more nodes” on line 16 of the claim, which renders the claim indefinite because it is unclear whether one or more nodes refer to the one or more nodes on line 14 or to another nodes. Appropriate correction is required.
Claims 2-5 are rejected for dependency upon rejected base claim 1 above.
Claim 1 recites the limitation “one or more nodes” on line 18 of the claim, which renders the claim indefinite because it is unclear whether one or more nodes refer to the one or more nodes on line 14 or to another nodes. Appropriate correction is required.
Claims 2-5 are rejected for dependency upon rejected base claim 1 above.
Claim 6 recites the limitation “an accelerator” on line 3 of the claim, which renders the claim indefinite because it is unclear whether the accelerator refers to the accelerator on line 1 of the claim or to another. Therefore, the limitation “an accelerator” on line 3 of the claim is interpreted as “the accelerator”.
Claims 7-13 are rejected for dependency upon rejected base claim 6 above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes, the memory including instructions executable by the processor to: retrieve, at the processor and for a failed node of the coarse-grained reconfigurable array, information about a predecessor node and a successor node of the failed node; create data structures to hold current positions and possible positions of the failed node based on the predecessor node and the successor node; update a mapping of the predecessor node or the successor node connected to the failed node; re-map one or more nodes that share a timeslot with the failed node; re-map one or more nodes that share a timeslot with the predecessor node; and re-map one or more nodes that share a timeslot with the successor node.
The limitations of updating a mapping and remapping steps, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a processor” and “a memory” nothing in the claim elements precludes the step from practically being performed in the mind. For example, but for the “processor” and “memory” language, updating a mapping and remapping steps in the context of these claims encompasses a user mentally mapping information. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” groupings of abstract ideas. Accordingly, claim 1 recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional steps of a processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes, retrieving information and creating data structures.
The processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes are recited at a high level of generality and amounts to mere instructions to apply/using the computer as a tool. The retrieving step is recited at a high level of generality and amounts to mere data gathering, which is a form of insignificant extra-solution activity. The creating step is recited at a high level of generality and amounts to mere storing, which is a form of insignificant extra-solution activity.
The combination of these additional steps are no more than mere instructions to apply the exception using generic computer components (i.e. the processor and memory). Accordingly, even in combination, these additional steps do not integrate the abstract idea into a practical application because they do not impose meaningful limits on practicing the abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the processor is a generic computer processor which performs the processor in communication, retrieving and creating steps. The additional elements of retrieving and creating steps which is insignificant extra-solution activity (MPEP 2106.05(d) and WURC as data gathering and storing, respectively, which is covered by court cases in MPEP 2106.05(g)). Claim 1 is not patent eligible.
Claim 2 recites "iteratively update mappings for predecessor nodes and/or mappings for successor nodes of the failed node based on the re-mapping" (mental processes). The features of this claim do not add any additional elements integrating the abstract idea into a practical application or amounting to significantly more.
Claim 3 recites "iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the failed node based on the re-mapping" (mental processes). The features of this claim do not add any additional elements integrating the abstract idea into a practical application or amounting to significantly more.
Claim 4 recites "iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the predecessor node based on the re-mapping" (mental processes). The features of this claim do not add any additional elements integrating the abstract idea into a practical application or amounting to significantly more.
Claim 5 recites "iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the successor node based on the re-mapping" (mental processes). The features of this claim do not add any additional elements integrating the abstract idea into a practical application or amounting to significantly more.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sunada (US 8,589,441).
Per Claim 6:
Sunada teaches:
- initiating a mapping of scheduled operations for a plurality of nodes associated with processing element (PEs) of an accelerator; identifying a mapping failure for a problem node of the plurality of nodes; analyzing a predecessor node of the plurality of nodes and a successor node of the plurality of nodes associated with the problem node (“… Moreover, upon receipt of an instruction to change the access right from the edge node 10 of the successor, the core node 20 updates the access right of the edge node 10 of the successor stored in the core node 20 itself according to the instruction. Thus, the core node 20 can manage the access rights currently granted to the respective edge nodes 10. With this mechanism, an edge node 10 having a failure can be taken over by another edge node 10 surely. … In addition, during the normal period, the management apparatus 30 (or the core node 20) collects resource information of each edge node 10 and determines the aptitudes of the edge nodes 10 as a successor of the edge node 10 having a failure on the basis of the collected resource information to output the determination results of the aptitudes. Thus, when a failure occurs, an operator or the like can quickly complete takeover of the function of the edge node 10 having the failure by another edge node 10 by selecting the edge node 10 as the successor promptly and appropriately. … In the case of the edge node 10 configured as a disk array apparatus, the edge node 10 further includes, for example, a high-speed data transfer device (DMA (Direct Memory Access)), a cache memory, a channel controller, a disk controller, a RAID (Redundant Arrays of Inexpensive Disk) controller, a high-speed communication switch (crossbar switch) and the like. …” in column 6, lines 11-28 and lines 57-63)
- creating data structures for each node to hold its current position and possible positions based on the predecessor node and the successor node (“… the management apparatus 30 (or the core node 20) collects resource information of each edge node 10 and determines the aptitudes of the edge nodes 10 as a successor of the edge node 10 having a failure on the basis of the collected resource information to output the determination results of the aptitudes. Thus, when a failure occurs, an operator or the like can quickly complete takeover of the function of the edge node 10 having the failure by another edge node 10 by selecting the edge node 10 as the successor promptly and appropriately. …” in column 6, lines 19-28); and invoking one or more recovery routines to resolve the mapping failure based on the predecessor node and the successor node (“… FIG. 4 shows takeover performed by the information processing system 1 when the first edge node 10 has a failure. As shown in FIG. 4, when the first edge node 10 has a failure, the management apparatus 30 displays the takeover aptitudes of the respective edge nodes 10 and thereby prompts the operator to select an edge node 10 (S411). When the operator selects the edge node 10 as the successor, the management apparatus 30 sends the selected edge node 10 an instruction to take over the function of the first edge node 10 (hereinafter referred to as a first instruction) (S412). Here, FIG. 4 shows the case where the second edge node 10 is selected as the successor, and where the management apparatus 30 sends the first instruction to the second edge node 10. … Upon receipt of the first instruction, the second edge node 10 changes its own access right from "RO" to "RW" (S413). Moreover, the second edge node 10 sends the core node 20 an instruction to change its own access right (of the second edge node 20) managed by the core node 20 from "RO" to "RW" (hereinafter referred to as a second instruction) (S414). …” in column 5, lines 20-38 and column 6, lines 19-28).
Per Claim 7:
Sunada teaches:
- performing local adjustments to the scheduled operations relative to the problem node to resolve the mapping instead of backtracking or restarting the mapping to resolve the mapping failure (column 5, lines 25-38).
Per Claim 8:
Sunada teaches:
- starting the mapping in a reverse breadth-first search graph traversal to aid the mapping of predecessors (column 5, lines 38-44).
Per Claim 9:
Sunada teaches:
- wherein the plurality of nodes are prescheduled to a timeslot before the mapping (column 5, lines 6-19).
Per Claim 10:
Sunada teaches:
- wherein the one or more recovery routines includes making changes to the predecessor node or the successor node connected to the problem node (column 5, lines 33-48).
Per Claim 11:
Sunada teaches:
- wherein the one or more recovery routines includes remapping of nodes sharing a timeslot of the problem node (column 5, lines 45-59).
Per Claim 12:
Sunada teaches:
- wherein the one or more recovery routines includes timeslot level remapping of nodes in timeslots associated with the predecessor node and the successor node (column 5, lines 45-59).
Per Claim 13:
Sunada teaches:
- wherein the initiating of the mapping of scheduled operations for the plurality of nodes includes timeslot level remapping where nodes mapped to a current node's timeslot are taken and for each of already mapped nodes local remapping is performed (column 5, lines 45-67).
Per Claims 14-16:
These are medium versions of the claimed method discussed above (claims 6-8, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, these claims are also anticipated by Sunada.
Per Claim 17:
Sunada teaches:
- wherein the one or more recovery routines includes exploring local transformations for the
predecessor node and the successor node to determine a reason for the mapping failure (column 4, line 54 to column 5, line 19).
Per Claim 18:
Sunada teaches:
- wherein the one or more recovery routines includes iterative exploration of different processing element positions of other nodes in the time-slot of the problem node, the predecessor node, and the successor node (column 5, lines 20-52).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sunada (US 8,589,441) in view of Rister (US 2023/0315406).
Per Claim 1:
Sunada teaches retrieve, at the processor and for a failed node of the array, information about a predecessor node and a successor node of the failed node (“… Moreover, upon receipt of an instruction to change the access right from the edge node 10 of the successor, the core node 20 updates the access right of the edge node 10 of the successor stored in the core node 20 itself according to the instruction. Thus, the core node 20 can manage the access rights currently granted to the respective edge nodes 10. With this mechanism, an edge node 10 having a failure can be taken over by another edge node 10 surely. … In the case of the edge node 10 configured as a disk array apparatus …” in column 6, lines 11-18 and lines 57-63); create data structures to hold current positions and possible positions of the failed node based on the predecessor node and the successor node (“… the management apparatus 30 (or the core node 20) collects resource information of each edge node 10 and determines the aptitudes of the edge nodes 10 as a successor of the edge node 10 having a failure on the basis of the collected resource information to output the determination results of the aptitudes. Thus, when a failure occurs, an operator or the like can quickly complete takeover of the function of the edge node 10 having the failure by another edge node 10 by selecting the edge node 10 as the successor promptly and appropriately. …” in column 6, lines 19-28); update a mapping of the predecessor node or the successor node connected to the failed node (“… FIG. 4 shows takeover performed by the information processing system 1 when the first edge node 10 has a failure. As shown in FIG. 4, when the first edge node 10 has a failure, the management apparatus 30 displays the takeover aptitudes of the respective edge nodes 10 and thereby prompts the operator to select an edge node 10 (S411). When the operator selects the edge node 10 as the successor, the management apparatus 30 sends the selected edge node 10 an instruction to take over the function of the first edge node 10 (hereinafter referred to as a first instruction) (S412). Here, FIG. 4 shows the case where the second edge node 10 is selected as the successor, and where the management apparatus 30 sends the first instruction to the second edge node 10. … Upon receipt of the first instruction, the second edge node 10 changes its own access right from "RO" to "RW" (S413). Moreover, the second edge node 10 sends the core node 20 an instruction to change its own access right (of the second edge node 20) managed by the core node 20 from "RO" to "RW" (hereinafter referred to as a second instruction) (S414). …” in column 5, lines 20-38 and column 6, lines 19-28); re-map one or more nodes that share a timeslot with the failed node; re-map one or more nodes that share a timeslot with the predecessor node; and re-map one or more nodes that share a timeslot with the successor node (column 5, lines 45-67). Sunada does not explicitly teach a processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes, the memory including instructions executable by the processor.
However, Rister teaches a processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes, the memory including instructions executable by the processor (par. 0082).
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the system disclosed by Sunada to include a processor in communication with a memory and a coarse-grained reconfigurable array having a plurality of nodes, the memory including instructions executable by the processor using the teaching of Rister. The modification would be obvious because one of ordinary skill in the art would be motivated to optimize allocation of hardware resources for a computing system (Rister, par. 0017).
Per Claim 2:
The rejection of claim 1 is incorporated, and Rister further teaches iteratively update mappings for predecessor nodes and/or mappings for successor nodes of the failed node based on the re-mapping (par. 0181-0185).
Per Claim 3:
The rejection of claim 1 is incorporated, and Rister further teaches iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the failed node based on the re-mapping (par. 0181-0185).
Per Claim 4:
The rejection of claim 1 is incorporated, and Rister further teaches iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the predecessor node based on the re-mapping (par. 0181-0184).
Per Claim 5:
The rejection of claim 1 is incorporated, and Rister further teaches iteratively update predecessor nodes and/or successor nodes of the one or more nodes that share a timeslot with the successor node based on the re-mapping (par. 0183-185).
Per Claim 19:
The rejection of claim 14 is incorporated, and further, Sunada does not explicitly teach wherein the accelerator is a coarse-grained reconfigurable array (CGRA) including a compiler.
However, Rister teaches wherein the accelerator is a coarse-grained reconfigurable array (CGRA) including a compiler (par. 0082-0083).
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the medium disclosed by Sunada to include wherein the accelerator is a coarse-grained reconfigurable array (CGRA) including a compiler using the teaching of Rister. The modification would be obvious because one of ordinary skill in the art would be motivated to optimize allocation of hardware resources for a computing system (Rister, par. 0017).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sunada (US 8,589,441) in view of Martin (US 2006/0048123).
Per Claim 20:
The rejection of claim 19 is incorporated, and further, Sunada does not explicitly teach wherein the compiler is a Modulo Scheduling-based compiler.
However, Martin teaches wherein the compiler is a Modulo Scheduling-based compiler (par. 0050-0051 and e.g see pg. 8, claim 5).
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the medium disclosed by Sunada to include wherein the compiler is a Modulo Scheduling-based compiler using the teaching of Martin. The modification would be obvious because one of ordinary skill in the art would be motivated to schedule instructions to generate desired and optimal schedules (Martin, par. 0013).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Morris (US 2016/0162547) teaches a method for mapping data to multiple processing units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QAMRUN NAHAR whose telephone number is (571)272-3730. The examiner can normally be reached Monday - Friday 8-4pm.
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/QAMRUN NAHAR/Primary Examiner, Art Unit 2199