Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-18, drawn to a semiconductor device in the reply filed on 08/10/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, all of the claimed “recessed portions” must be illustrated and, preferably, labeled or the features canceled from the claims. Particularly, the position of the third recessed portion must be indicated in the drawings (see the 112(b) rejection of claim 2 below. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding claim 2 - this claim depends on claim 1, so it includes the limitation that the semiconductor device comprises a first electrode that has an upper surface that includes a third recessed portion located immediately above the opening. Claim 2 teaches that the third recessed portion is further provided immediately above the second recessed portion in the upper surface of the first electrode. This configuration is not geometrically possible – the third recessed portion cannot be positioned so that it is immediately above the opening and immediately above the second recessed portion in the upper surface of the first electrode because, according to the disclosure, the opening and the second recessed portion are not immediately above one another. It is not possible to reject this claim with prior art as, according to the disclosure, the configuration of elements claimed is impossible. As examined below the claim will be interpreted as stating “wherein the third recessed portion is further provided above the second recessed portion in the upper surface of the first electrode.” (losing the phrase ‘immediately above’ to simply be ‘above’).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 12, 13, 15, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzawa US 20220028735.
Regarding claim 1, Suzawa discloses a semiconductor device comprising:
a plurality of trenches provided on an upper surface of a semiconductor substrate (figure 1 shows a plurality of trenches 5 are provided on the upper surface of substrate 10) ;
a plurality of trench electrodes provided respectively inside the plurality of trenches (figure 1 shows electrodes 7 in trenches 5);
an insulation film that covers two or more trench electrodes among the plurality of trench electrodes (figure 1, insulation film 13 covers 2 or more trenches); and
a first electrode provided on the insulation film (electrode 15/16 is provided on insulation film 13),
wherein the insulation film has an opening provided between the two or more trench electrodes covered with the insulation film (see the opening w2’ in figure 1),
the first electrode is provided on the semiconductor substrate to fill the opening (figure 1 shows electrode 15/16 is provided on the semiconductor substrate 10 and fills the opening w2’),
each of the plurality of trench electrodes has an upper surface that includes a first recessed portion (see annotated figure 1),
the insulation film has an upper surface that includes a second recessed portion located immediately above the first recessed portion (see annotated figure 1), and
the first electrode has an upper surface that includes a third recessed portion located immediately above the opening (see annotated figure 1).
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Regarding claim 2, Suzawa discloses wherein the third recessed portion is further provided above the second recessed portion in the upper surface of the first electrode (see annotated figure above - 3rd recessed portion is vertically above the second recessed portion).
Regarding claim 3, Suzawa discloses the semiconductor device according to claim 1, further comprising: a second electrode provided on the first electrode, wherein the second electrode has an upper surface that includes a fourth recessed portion located immediately above the third recessed portion. (Second electrode 17 is provided on the first electrode 15/16. The second electrode has an upper surface that includes a fourth recessed portion, as indicated on annotated figure 1 This second electrode’s upper surface, which comprises the fourth recessed portion, is located immediately above the third recessed portion, as illustrated in annotated figure 1 used for the rejection of claim 1).
Regarding claim 4, Suzawa discloses the semiconductor device according to claim 3, wherein the fourth recessed portion has a shallower depth than the third recessed portion. (See annotated figure 1 below, where the depths of the fourth recessed portion and the third recessed portion are indicated. The fourth recess portion has a shallower (smaller) depth than the third recessed portion.)
Regarding claim 5, Suzawa discloses the semiconductor device according to claim 4, wherein the depth of the fourth recessed portion is shallower than a depth of the opening. (See annotated figure 1 below, where the depth of the fourth recessed portion and the depth of the opening are indicated. The fourth recess portion has a shallower (smaller) depth than the depth of the opening.)
Regarding claim 6, Suzawa discloses the semiconductor device according to claim 5, wherein the depth of the fourth recessed portion is shallower than a depth of the first recessed portion. (See annotated figure 1 below, where the depths of the fourth recessed portion and the first recessed portion are indicated. The fourth recess portion has a shallower (smaller) depth
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than the first recessed portion.)
Regarding claim 7, Suzawa discloses the semiconductor device according to claim 1, wherein the first recessed portion has a bottom located at a lower level than the upper surface of the semiconductor substrate (see annotated figure 1 below).
Regarding claim 8, Suzawa discloses the semiconductor device according to claim 1, wherein each of the plurality of trench electrodes has an upper end located at a lower level than the upper surface of the semiconductor substrate (see annotated figure 1 used for the rejection of
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claim 7).
Regarding claim 9, Suzawa discloses the semiconductor device according to claim 1, wherein the insulation film has a single-layer structure that includes an oxide film (see figure 1, element 6, which is an oxide film [0059]).
Regarding claim 10, Suzawa discloses the semiconductor device according to claim 1,wherein the insulation film has a laminated structure that includes two or more types of oxide films having different dopant concentrations (Paragraph [0061] discloses that the insulation layer comprises two oxide films, where the upper layer 12 is a BPSG film and the lower layer 11 is a HTO film. These layers have different doping concentrations, as BPSG is doped with phosphorous and boron, while HTO film is intrinsically undoped.)
Regarding claim 12, Suzawa discloses the semiconductor device according to claim 3, wherein the second electrode has a greater thickness than the first electrode (The claimed relationship of layer thicknesses is shown in annotated figure 1 below.).
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Regarding claim 13, Suzawa discloses the semiconductor device according to claim 1, wherein the opening has a bottom having a width greater than a height of the insulation film that forms a side wall of the opening (The claimed relationship between the width of the bottom of the opening and the height of the insulation film forming the sidewall of the opening is shown in annotated figure 1 below).
Regarding claim 15, Suzawa discloses the semiconductor device according to claim 1, wherein the first electrode is in contact with the upper surface of the semiconductor substrate at a bottom of the opening (annotated figure 1 below shows that first electrode 15/16 is in contact with the upper surface of semiconductor substrate 10 at the bottom of the opening).
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Regarding claim 16, Suzawa discloses the semiconductor device according to claim 1, wherein each of the two or more trench electrodes covered with the insulation film is a gate electrode of an insulated gate bipolar transistor (IGBT) formed on the semiconductor substrate (paragraph [0059] discloses wherein the embodiment depicted in figure 1 is a trench-gate IGBT).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Suzawa.
Regarding claim 11, Suzawa discloses the semiconductor device according to claim 3. Suzawa lacks wherein the first electrode has a greater thickness than the second
electrode.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to vary the thicknesses (sizes and proportions) of the first and second electrode layers in order to optimize the device by, for example, reducing the switching speed.
Claims 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suzawa in view of Hondo WO2023/157395 (where Hondo US 20240405109 is used as a translation and all citations pointed to below).
Regarding claim 13, Suzawa discloses the semiconductor device according to claim 3.
Suzawa lacks wherein the second electrode has a laminated structure that includes two or more types of metal layers.
However, Hondo discloses an analogous IGBT device wherein the second electrode (figure 8, layer 90) may have a laminated structure including a plurality of metal films, 91 and 92 (paragraph [0145]), and the layers 91 and 92 may include different metals [0161].
Therefore, it would have been obvious to a person having ordinary skill in the art before the date of filing to create a multilayer metal electrode to balance electrical and mechanical properties, such as improving adhesion with one metal layer and improving diffusion barrier performance by means of different metal layer.
Regarding claim 17, Suzawa discloses the semiconductor device according to claim 1, including a plurality of trench electrodes (5, figure 1), a plurality of first trench electrodes (5, figure 1) serving as the two or more trench electrodes and covered with the insulation film (13, figure 1).
Suzawa lacks wherein the plurality of trench electrodes includes: at least one second trench electrode provided on an inner side of the opening of the insulation film, each of the plurality of first trench electrodes is a gate electrode of an insulated gate bipolar transistor (IGBT) formed on the semiconductor substrate, the at least one second trench electrode is not covered with the insulation film and is electrically connected to the first electrode, and
the first recessed portion in the upper surface of the at least one second trench electrode forms part of a bottom of the opening.
However, Hondo discloses an analogous IGBT device wherein the plurality of trench electrodes include:
a plurality of first trench electrodes serving as the two or more trench electrodes and covered with the insulation film (paragraphs [0048 – 0049] and figures 4 and 8 disclose a plurality of first trench electrode structures 20, comprising trench electrodes 23]); and
at least one second trench electrode provided on an inner side of the opening of the insulation film (Hondo’s third electrode structures 50, comprising electrodes 53, are provided on an inner side of the opening of the insulation film 73, figure 8 and [0091-0092]),
each of the plurality of first trench electrodes is a gate electrode of an insulated gate bipolar transistor (IGBT) formed on the semiconductor substrate paragraph [0039],
the at least one second trench electrode is not covered with the insulation film and is electrically connected to the first electrode (figure 8 shows that at least one second trench electrode 53 is connected to second electrode 91/92, which is electrically connected to first electrode 80) and
the first recessed portion in the upper surface of the at least one second trench electrode forms part of a bottom of the opening (figure 8 shows that the upper surface of the recessed portion of the gate electrode 53 forms part of the bottom of the opening in the insulation layer 73).
Therefore, it would have been obvious to a person having ordinary skill in the art to include Hondo’s third electrode structure in a device having the IGBT structure of Suzawa to provide a reverse conduction path while producing a more compact device.
Regarding claim 18, Suzawa as modified by Hondo discloses the semiconductor device according to claim 17, wherein
the at least one second trench electrode is formed inside each of the plurality of trenches via a trench insulation film provided along an inner wall of each of the plurality of trenches (figure 8 shows the second plurality of trenches 51 with a trench insulation film 52 [0090] and a trench electrode 53 [0091]), and
the trench insulation film that is in contact with the at least one second trench electrode has an upper surface that includes a fifth recessed portion located below the upper surface of the semiconductor substrate (see annotated figure 8 below).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yamamoto et al. US 5714781 discloses a semiconductor device with multiple intentionally recessed or indented surfaces; Konishi US 20230335604 discloses an IGBT device capable of efficiently discharging carriers to an emitter during turn-off; Kuruc et al. US 20140027813 discloses an IGFET device that reduces gate capacitance..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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