DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the rejection of the claims have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8-9, 11-14, 18-22, and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Whetel (US 8,464,112) and further in view of Wang et al., "A Case Study of Hierarchical Diagnosis for Core-Based SoC" by Wang et al., ECS Transactions, 2010.
Claim 1: Whetel teaches an integrated circuit, comprising:
a first block including a first wrapper and a first area of circuit elements isolated by the first wrapper (e.g., Whetel teaches core 1 (element 1001) with wrapper 1002 that isolates its core logic area. The wrapper "resides at the boundary of a core and provides a way to test the core." See col. 1, ll. 21-23; Fig. 10);
a target block, which includes a second wrapper and a second area of circuit elements isolated by the second wrapper, and a third wrapper and a third area of circuit elements isolated by the third wrapper (e.g., Whetel teaches core 4 (target block 1001) containing embedded core A (1003) with wrapper 1004 isolating its logic, and embedded core B (1005) with wrapper 1006 isolating its logic. See col. 8, ll. 35-45; Fig. 10); and
a second block including a fourth wrapper and a fourth area of circuit elements isolated by the fourth wrapper(e.g., Whetel teaches additional cores (e.g., core 2, core 3 in Fig. 13) each with wrappers. See Fig. 13);
wherein the second wrapper is connected in series with the first wrapper, and is configured to perform a test operation on the second area (e.g., Whetel explicitly shows wrappers 307-309 connected in series and configured to test core logic via internal scan registers. See, col. 2, ll. 30-35 ("internal scan register 108 is part of the core circuitry that may be accessed via the wrapper for testing the core"); Fig. 3, col. 2, ll. 40-45);
wherein the third wrapper is connected in series with the fourth wrapper, and is configured to perform a test operation on the third area (e.g., Whetel's architecture supports multiple serial wrapper chains, as shown in Figs. 7 and 13-14. One of ordinary skill would recognize that core B's wrapper could be connected to a downstream wrapper);
wherein the first block is configured to receive a test signal, and the first wrapper included in the first block is configured to input the test signal to the second area of circuit elements included in the target block (e.g., Whetel teaches that wrappers can apply test stimuli to core logic. Fig. 1 shows test data being shifted into data registers (including internal scan register) via SI. Wang confirms this arrangement, showing wrapper cells at core boundaries that launch signals into core logic);
wherein the second wrapper is configured to receive the test signal after the test signal has been input to the second area of circuit elements by the first wrapper and has passed through the second area of circuit elements (e.g., This describes interconnect testing between cores, which Whetel explicitly teaches: the wrapper "provides a way to test the core and the interconnections between cores." See col. 1, ll. 23-24).
Not explicitly taught by Whetel is that: wherein the first area is an edge area of the first block positioned between the first wrapper and the second wrapper;
wherein the second area is an edge area of the target block positioned between the first wrapper and the second wrapper;
wherein the third area is another edge area of the target block positioned between the third wrapper and the fourth wrapper; and
wherein the fourth area is an edge area of the second block positioned between the third wrapper and the fourth wrapper.
However, Wang's wrapper cell design (Figure 2) places wrapper cells at core boundaries, with the core logic positioned between input wrapper cells and output wrapper cells. When cores are arranged hierarchically as in Whetel's Figure 13, the logic of a core inherently forms an "edge area" positioned between the wrapper that precedes it in the serial path and the wrapper that follows it. The claim's "edge area" language merely describes the physical arrangement necessarily present in Whetel's hierarchical wrapper architecture when one considers the positional relationship of cores and their wrappers. Wang's teaching that wrapper cells reside at core boundaries confirms that the core logic is the "area" between input and output wrapper cells. See Section 2, Figures 2(b)-2(c).
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to look to Wang's simplified wrapper design to reduce area overhead while implementing Whetel's hierarchical access scheme.
Claim 2: Whetel and Wang teach the integrated circuit of Claim 1, wherein the first and second wrappers are configured to share a wrapping signal, which is received as an input from external the integrated circuit. For instance, Whetel explicitly teaches that the test interface signals 109 (which include wrapping signals such as clock, shift, capture, update) are "bussed to the CTL-1, CTL-2, and CTL-3 inputs of wrappers 307-309" (e.g., col. 2, ll. 40-45; Fig. 3). This bussing arrangement means the first and second wrappers share common wrapping signals. Whetel further teaches that "[a]ccess to the SI 302, SO 303, and test interface signals 109 of the arrangement 301 is typically provided to tester external of the IC" (e.g., col. 2, ll. 45-48), confirming the signals are received from external the integrated circuit. Wang similarly teaches wrapper control signals (WIP) including WRCK, CaptureWR, ShiftWR, UpdateWR that are shared among wrappers (e.g., Section 2; Fig. 1).
Claim 3: Whetel and Wang teach the integrated circuit of Claim 1, wherein the third and fourth wrappers are configured to share a wrapping signal, which is received as an input from external the integrated circuit. For instance, Whetel's test architecture applies the same bussing arrangement to all wrappers in the serial chain. Figures 6A and 13 show that all wrappers (including those designated as third and fourth wrappers in the hierarchical context) receive common control signals from the CTL bus 109 (e.g., Whetel, Figs. 6A, 13). The test interface signals are "bussed to the CTL-1, CTL-2, and CTL-3 inputs of wrappers 307-309" (e.g., col. 2, ll. 40-45), which would apply equally to additional wrappers in the hierarchy. Wang's architecture likewise shares wrapper control signals among all wrapped cores (e.g., Section 2; Fig. 1).
Claim 4: Whetel and Wang teach the integrated circuit of Claim 1, wherein the first, second, third, and fourth wrappers are each configured to include a plurality of register circuits, and to share a wrapping signal. For instance, Whetel teaches that each wrapper includes "an instruction register 105, and set of data registers 106-108" including an internal scan register, boundary scan register, and bypass register (e.g., col. 1, ll. 52-60; Fig. 1). These are clearly "a plurality of register circuits." Whetel further teaches that the wrappers share test interface signals 109 via bussing (e.g., col. 2, ll. 40-45; Fig. 3). Wang confirms that wrapper cells include multiple registers (flip-flops) and share control signals (e.g., Section 2, Figs. 2(b)-2(c)).
Claim 5: Whetel and Wang teach the integrated circuit of Claim 1, wherein the first, second, third, and fourth wrappers are configured to pass an input signal therethrough, when in an inactive state. For instance, Whetel explicitly teaches wrapper bypass functionality. Figure 1 shows a "bypass register 106 for bypassing the wrapper via a single bit" (e.g., col. 1, l. 66). When a wrapper is in bypass mode (inactive for testing that particular core), it "pass[es] an input signal therethrough" via the bypass register. Whetel also teaches enable/disable circuitry (FIG. 4) where "a low on enable 402 will disable the wrapper from responding to the test interface 109" (e.g., col. 2, ll. 65-67), which would place the wrapper in an inactive state where it simply passes signals through. Wang teaches the bypass register (WBY) that "provides a minimum length scan path through the wrapper" (e.g., Section 2(4)), confirming that wrappers can pass signals through when not actively testing.
Claim 8: Whetel and Wang teach the integrated circuit of Claim 1, wherein during a security mode of operation, the second wrapper and the third wrapper are each configured to receive a security signal and block an input signal. For instance, Wang teaches that in functional mode, wrappers can be configured to allow normal operation (e.g. Section 2: "in functional mode, 'test_mode' is set to 0 and the wrapper cell is in transparent mode"). The converse, blocking signals during a protected mode would have been an obvious extension to one of ordinary skill seeking to implement security features in a test architecture. Using enable/disable circuitry (as taught by Whetel's FIG. 4) to block signals during a security mode is a routine design choice.
As per claim 18, the claimed limitations are rejected similarly to claim 8 above.
Claim 9: Whetel and Wang teach the integrated circuit of Claim 4, wherein each of the plurality of register circuits includes: a first multiplexer configured to receive a data shift enable signal; a second multiplexer configured to receive a data capture enable signal; and a first flip-flop configured to extract captured data; and wherein in each of the plurality of register circuits, the first multiplexer is directly connected to the second multiplexer, and the first flip-flop is connected to the second multiplexer. For instance, Wang explicitly teaches this exact wrapper cell structure. Figure 2(b) and 2(c) show wrapper cells at core output and input sides, respectively, with multiplexers and flip-flops arranged as claimed. The wrapper cell circuits include multiplexers controlled by "wrapper_se" (shift enable) and other control signals, with flip-flops for capturing data. Wang describes that "by using two flops per wrapper cell, core IOs can be used as launched points for at-speed test" (e.g., Section 2). The Chinese article provides additional implementation detail showing the same multiplexer/flip-flop structure in P1500 wrapper cells. Whetel's FIG. 1 shows multiplexers 104 and gates 101-102 that perform similar selection functions.
As per claim 19, the claimed limitations are rejected similarly to claim 9 above.
Claims 11-14 recite a memory device comprising an integrated circuit with substantially the same structural limitations as claims 1-4, with minor variations in claim language. For the reasons set forth in the rejection of claims 1-4, these claims are obvious.
Claim 20 is a method claim reciting steps that directly correspond to the structural operations of claim 1. Whetel teaches inputting test signals, forming wrapper chains, receiving signals after propagation through core logic, and extracting output values (e.g., Figs. 1, 3, 7, 13). And Wang's hierarchical diagnosis flow confirms these testing operations (e.g., Sections 3-4).
Claim 21: Whetel and Wang teach the integrated circuit of Claim 1, wherein the first wrapper is further configured to input the test signal to the first area of circuit elements included in the first block. For instance, Whetel explicitly teaches that wrappers can test their own core logic via internal scan registers. Figure 1 shows the internal scan register 108, which is "part of the core circuitry that may be accessed via the wrapper for testing the core" (e.g., col. 2, ll. 30-35). This capability is inherent in wrapper functionality; a wrapper is designed both to test its own core (internal testing) and to test interconnections between cores. Wang confirms this dual functionality, teaching that the wrapper boundary register allows "internal testing of the core, as well as testing of external connectivity to other cores" (e.g., Section 2(5)).
Claim 22: Whetel and Wang teach the integrated circuit of Claim 1, wherein the second area of circuit elements is isolated by both the first wrapper and the second wrapper. This limitation describes the inherent positional relationship in Whetel's hierarchical architecture. As shown in Figures 10 and 13, when a first wrapper (e.g., wrapper of core 1) drives a target core's logic (core 4's logic), and a second wrapper (e.g., wrapper of embedded core A within core 4) captures the output, the logic of the target core is necessarily positioned between; and thus operationally "isolated by" both wrappers in the sense that it lies between them in the test path. Wang's boundary cell placement (e.g., Fig. 2) confirms that core logic is positioned between input wrapper cells (which launch signals) and output wrapper cells (which capture signals). The claimed "isolated by both" language merely describes this spatial and functional relationship inherent in the hierarchical test architecture.
Claim 24: Whetel and Wang teach the method of Claim 20, wherein the target block is external to the first block; and wherein the second block is external to the target block. This describes the hierarchical relationship already present in Whetel's Figures 10-14. Core 4 (target block) is external to and distinct from core 1 (first block). Core 2 and core 3 (second blocks) are external to and distinct from core 4. The hierarchical arrangement of blocks external to one another is fundamental to Whetel's disclosure of embedded cores within a larger core (e.g., Figs. 10-14). Wang's discussion of core-based SoC design confirms that embedded cores are distinct blocks external to one another within the chip hierarchy (e.g., Section 1).
Claim 25: Whetel and Wang teach the memory device of Claim 11, further comprising one or more top level logic circuits configured to drive circuitry to be tested. For instance, Whetel's test interface 109 and control bus provide top-level control logic for driving test operations to all wrappers (e.g., Figs. 1, 6A, 8A). The test interface signals include clock, shift, capture, update, reset, and select signals that "drive circuitry to be tested." Whetel further teaches that access to these signals is "provided to tester external of the IC" (e.g., col. 2, ll. 45-48), and the Link Instruction Register (LIR) 801 provides additional top-level control logic (e.g., Fig. 8A). Wang similarly discloses a "CTAP controller" and "test configuration registers" that serve as top-level logic circuits for driving test operations (e.g., Sections 2.2-2.3 and reference 6).
Claim 26: Whetel and Wang teach the integrated circuit of Claim 1, wherein the first wrapper included in the first block is configured to input the test signal to the second area of circuit elements included in the target block via one or more output terminals of the first block; and wherein the target block is external to the first block. This limitation merely adds detail to the test signal flow already described in claim 1 and shown in Whetel's Figures 1, 3, and 13. For a first wrapper to input a test signal to a target block's logic, the signal must necessarily pass through output terminals of the first block. This is inherent in the physical architecture of separate blocks. Whetel's wrapper design includes output terminals (serial output SO) and boundary cells that interface with core I/O (e.g., Fig. 1, col. 1, ll. 60-65). Wang's wrapper cells at core boundaries (e.g., Figs. 2(b)-2(c)) confirm that test signals are input via output terminals. The target block being external to the first block is already established in Whetel's hierarchical arrangement (e.g., Figs. 10-14).
Claim 27: Whetel and Wang teach the integrated circuit of Claim 1, wherein the second wrapper is configured to receive the test signal after the test signal has been input to the second area of circuit elements by the first wrapper and has passed through the second area of circuit elements, without the second wrapper having input the test signal to the second area of circuit elements. This limitation describes the standard interconnect test mode where one wrapper launches a test signal into core logic and another wrapper captures the result after propagation. The second wrapper acts solely as a receiver/capturer, not as a launch point for that particular test signal. This is inherent in Whetel's teaching that wrappers test "interconnections between cores" (e.g., col. 1, ll. 23-24). In interconnect testing, a first wrapper drives a signal through core logic, and a second wrapper observes the result without itself driving that signal. Wang confirms this distinction, teaching that wrapper boundary cells can be configured as input cells (launch) or output cells (capture) depending on the test mode (e.g., Section 2, Figs. 2(b)-2(c)). The claim's "without the second wrapper having input the test signal" merely excludes the launch function for that particular test operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/23/2026