DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "thickness direction" in Claim 3 Line 4. There is insufficient antecedent basis for this limitation in claim 2 and claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Su(US11658220B2) and Chen(US20220013453A1).
Regarding Claim 1, Su teaches in Fig 2 a semiconductor device comprising:
an insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) comprising:
a first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65);
a second surface (FIG 2 with annotations; 126; second surface; Col 5 Ln 61-65); and
an element isolation trench (FIG 2; 220; Col 6 Ln 15-19);
an insulating pattern (FIG 2; 127; Col 6 Ln 54-58) on the first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65) of the insulating layer (FIG 2; 126; Col 5 Ln 61-65);
an active pattern on the insulating pattern and comprising a channel pattern (FIG 102; Col 3 Ln 56-58);
a source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) on at least one side of the active pattern (FIG 102; Col 3 Ln 56-58);
a lower wiring structure (FIG 2; 216; Col 17 Ln 34-37) on the second surface of the insulating layer (FIG 2; 212; Col 17 Ln 34-38); and
a through-via (FIG 2; 218; Col 4 Ln 39-44) that extending in the insulating layer and connecting the source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) and the lower wiring structure (FIG 2; 216; Col 17 Ln 34-37),
wherein the insulating pattern comprises:
a first portion (FIG 2; 127; Col 6 Ln 54-58) between the insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) and the active pattern (FIG 102; Col 3 Ln 56-58);
a third portion (FIG 2; 210; Col 12 Ln 36-40) on a bottom surface of the element isolation trench.
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Su does not teach a second portion surrounding at least a portion of the through-via; and
Chen teaches in FIG 2B a second portion (FIG 2B; 269; ¶[0029]) surrounding at least a portion of the through-via (FIG 2B; 358; ¶[0016]); and
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via, and the prior art of Chen, a semiconductor transistor with a dielectric layer surrounds a portion of the through-via. This combination produces a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via with a dielectric layer surrounds a portion of the through-via. The dielectric material surrounding the trough via prevents electrical leakage during electron movement through the transistor Chen(¶[0029]).
Regarding Claim 2, Su and Chen teach the semiconductor device of claim 1.
Su teaches in FIG 2 wherein the third portion of the insulating pattern (FIG 2; 210; Col 12 Ln 36-40) is on an inner wall of the element isolation trench (FIG 2; 220; Col 6 Ln 15-19),
Su and Chen do not teach and wherein a length of the second portion of the insulating pattern in the thickness direction of the insulating layer is smaller than a length of the third portion of the insulating pattern in the thickness direction of the insulating layer.
However, the ordinary artisan would have recognized the thickness of the insulation patter to be a result effective variable affecting flow of current in the device. Thus, it would have been obvious to limit the thickness of the insulating patterns within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding Claim 3, Su and Chen teach the semiconductor device of claim 2.
Su teaches in FIG 2, wherein a lower surface of the first portion of the insulating pattern (FIG 2 with annotations; first portion to second surface) is farther from the second surface of the insulating layer than a lower surface of the source/drain pattern is from the second surface of the insulating layer (FIG 2 with annotations; Source/drain pattern to second surface).
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Regarding Claim 4, Su and Chen teach the semiconductor device of claim 1.
Su teaches in Fig 2, wherein the second portion of the insulating pattern (FIG 2; 128; Col 6 Ln 13-15) contacts at least a portion of a side surface of the source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22).
Regarding Claim 5, Su and Chen teach the semiconductor device of claim 1.
Su teaches the lower wiring structure (FIG 2; 216; Col 17 Ln 34-37).
Su does not teach wherein the through-via comprises:
a first via portion at least partially surrounded by the second portion of the insulating pattern; and
a second via portion between the first via portion
Chen teaches in Fig 2B wherein the through-via comprises:
a first via portion (FIG 2B with annotations; First via portion) at least partially surrounded by the second portion (FIG 2B; 269; ¶[0029]) of the insulating pattern; and
a second via portion (FIG 2B with annotations; Second via portion) between the first via portion (FIG 2B with annotations; First via portion)
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with a lower wiring structure and the prior art of Chen, a semiconductor device with a via comprised of a first portion surrounded by an insulating pattern and a second via portion connect to the first via portion. This combination produces a semiconductor transistor device with a via comprised of a first portion surrounded by an insulating pattern and a second via portion connect to the first via portion. The portion of the via surrounded by the insulating pattern closest to the source, drain and gate reduces electrical leakage Chen(¶[0029]).
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Regarding Claim 6, Su and Chen teach the semiconductor device of claim 5,
Su does not teach wherein a width of the second via portion is greater than a width of the first via portion.
Chen teaches wherein a width of the second via portion (FIG 2B with annotations; Second via portion) is greater than a width of the first via portion (FIG 2B with annotations; First via portion).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with a lower wiring structure and the prior art of Chen, a semiconductor device with a via having a second portion with a wider with than the first portion. This combination produces a semiconductor transistor device with a via having a second portion with a wider with than the first portion. The wider second portion creates a larger surface area to contact the connecting materials/substrate beneath it compared to the thinner first portion that does not need a larger surface area contact Chen(¶[0029]).
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Regarding Claim 7, Su and Chen teach the semiconductor device of claim 5.
Su does not teach wherein at least a portion of the second portion of the insulating pattern extends over the second via portion in a direction parallel with the second surface of the insulating layer, and wherein at least another portion of the second portion of the insulating pattern does not extend over the second via portion in the direction parallel with the second surface of the insulating layer.
Chen teaches wherein at least a portion of the second portion (FIG 2B; 269; ¶[0029]) of the insulating pattern extends over the second via portion (FIG 2B with annotations; Second via portion; The insulation pattern in in contact with the top of the second portion of the via covering a surface area parallel to the second surface) in a direction parallel with the second surface of the insulating layer, and wherein at least another portion of the second portion (FIG 2B; 269; ¶[0029]) of the insulating pattern does not extend over the second via portion (FIG 2B with annotations; Second via portion) in the direction parallel with the second surface of the insulating layer.
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with a lower wiring structure and the prior art of Chen, a semiconductor device with an insulating pattern with a portion extending over the second via portion in a direction parallel with the second surface and another portion not extending over the second portion in the direction parallel with the second surface. This combination produces a semiconductor transistor with an insulating pattern with a portion extending over the second via portion in a direction parallel with the second surface and another portion not extending over the second portion in the direction parallel with the second surface. The portions of the insulating pattern that contact the second via parallel to the second surface isolate components of the system Chen(¶[0029]).
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Regarding Claim 8, Su and Chen teach the semiconductor device of claim 1.
Su teaches in Fig 2 further comprising: a gate structure (FIG 2; 104; Col 5 Ln 39-42) on the insulating pattern and at least partially surrounding the channel pattern (FIG 102; Col 3 Ln 56-58),
the first portion of the insulating pattern (FIG 2; 127; Col 6 Ln 54-58) and
Su does not teach wherein the active pattern further comprises a lower pattern between the gate structure.
Chen teaches in FIG 3B wherein the active pattern (FIG 3B; 215; ¶[0016]) further comprises a lower pattern (FIG 3B; 357; ¶[0016]) between the gate structure (FIG 3B; 240; ¶[0015]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with gate structure on the insulating pattern and at least partially surrounding the channel pattern, and the prior art of Chen, a semiconductor device wherein the active pattern comprises a lower pattern in contact with the gate structure. This combination produces a semiconductor transistor device with gate structure on the insulating pattern and at least partially surrounding the channel pattern wherein the active pattern comprises a lower pattern inContact with the gate structure. the gate structure. The layer that is part of the active layer, in contact with the gate structure to reduce contact resistance in the area surrounding the gate Chen(¶[0016]).
Regarding Claim 11, Su and Chen teach the semiconductor device of claim 1.
Su teaches in Fig 2, further comprising: a gate structure (FIG 2; 220; Col 6 Ln 17-19) on the insulating pattern (FIG 2; 127; Col 6 Ln 54-58) and at least partially surrounding the channel pattern (FIG 102; Col 3 Ln 56-58), wherein the first portion of the insulating pattern (FIG 2; 127; Col 6 Ln 54-58) contacts the gate structure (FIG 2; 220; Col 6 Ln 17-19).
Regarding Claim 12, Su and Chen the semiconductor device of claim 1.
Su teaches in Fig 2, wherein the insulating pattern (FIG 2; 127; Col 16 Ln 42-27;
S
i
O
2
) comprises a material having etch selectivity (
S
i
O
2
has a higer etch selectivity than Carbon nitride) to the insulating layer (FIG 2; 126 and 112; Col 6 Ln 4-6).
Regarding Claim 13, Su and Chen teach the semiconductor device of claim 12.
Su teaches wherein the insulating pattern (FIG 2; 127; Col 6 Ln 54-58) comprises at least one of SiN, SiON, SiCN, SiOC, SiOCN, and metal oxides (FIG 2; 127; Col 16 Ln 39-42).
Regarding Claim 14, Su and Chen teach The semiconductor device of claim 1.
Su teaches in FIG 2 wherein the insulating pattern further comprises:
an outer insulating pattern contacting (FIG 2; 127; Col 6 Ln 54-58) the insulating layer (FIG 2; 126; Col 5 Ln 61-65); and
an inner insulating pattern on the outer insulating pattern (FIG 2; 118; Col 15 Ln 45-49), and wherein the inner insulating pattern comprises at least one of SiN, SiON, SiCN, SiOC, SiOCN, AIN, and Al203 (FIG 2; 118; the layer is defined as a dielectric liner, all of the materials listed in Claim 14 are dielectric materials which are in scope of the reference).
Claims 9, 10 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Su(US11658220B2) and Chen(US20220013453A1) as applied to claim 1-8, and 11-14 above, and further in view of Lin(US20240120414A1) and Mukesh(US20240347423A1).
Regarding Claim 9, Su and Chen teach the semiconductor device of claim 8.
Su and Chen do no teach further comprising: a dummy source/drain pattern below the source/drain pattern, wherein the insulating pattern further comprises a fourth portion at least partially surrounding the dummy source/drain pattern.
Lin teaches in FIG 12 further comprising: a dummy source/drain pattern (FIG 12; 150; ¶[0048]) , wherein the insulating pattern further comprises a fourth portion (FIG 12; 124; ¶[0048]) at least partially surrounding the dummy source/drain pattern (FIG 12; 150; ¶[0048]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su and Chen, semiconductor devices comprising an insulating layer an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and the prior art of Lin, a semiconductor device with a dummy source/drain sounded by an insulating layer. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern. The purpose of the insulating pattern is to control the isolation of the electrical component in the device Lin[0045].
Lin does not teach below the source/drain pattern
Mukesh teaches in FIG 12 below the source/drain pattern (FIG 12; 124; ¶[0032])
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, Chen and Lin, a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern and the prior art of Mukesh, a semiconductor device with a sacrificial placeholder below the source/drain pattern. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern below the source/drain pattern in place of the placeholder position. The placeholder position aid in the uniformity of the semiconductor structure during the fabrication process (Mukesh¶[0032]).
Regarding Claim 10, Su, Chen, Lin and Mukesh teach the semiconductor device of claim 9.
Su and Chen do not teach wherein an upper surface of the dummy source/drain pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure is from the second surface of the insulating layer.
Lin teaches in FIG 12 dummy source/drain pattern (FIG 12; 150; ¶[0048])
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su and Chen, semiconductor devices comprising an insulating layer an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and the prior art of Lin, a semiconductor device with a dummy source/drain sounded by an insulating layer. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern. The purpose of the insulating pattern is to control the isolation of the electrical component in the device Lin[0045].
Lin does not teach wherein an upper surface of the pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure is from the second surface of the insulating layer.
Mukesh teaches in FIG 16 wherein an upper surface of the pattern (FIG 16 with annotations; 104; place holder; ¶[0031]) is closer to the second surface (FIG 16 with annotations; second surface) of the insulating layer than a lower surface of the gate structure (FIG 16; 341; ¶[0037]) is from the second surface (FIG 16 with annotations; second surface) of the insulating layer.
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It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, Chen and Lin, a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern and the prior art of Mukesh, a semiconductor wherein an upper surface of the pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure is from the second surface of the insulating layer. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern wherein an upper surface of the pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure is from the second surface of the insulating layer. The placeholder position with respect to the second surface of the insulating layer determines the methods and procedures used to fabricate the transistors in the semiconductor device to achieve uniformity (Mukesh¶[0032]).
Regarding Claim 15, Su teaches in Fig 2 a semiconductor device comprising:
an insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) comprising a first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65) and a second surface (FIG 2 with annotations; 126; second surface; Col 5 Ln 61-65);
an insulating pattern (FIG 2; 127; Col 6 Ln 54-58) on the first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65) of the insulating layer (FIG 2; 126; Col 5 Ln 61-65);
an active pattern on the insulating pattern and comprising a channel pattern (FIG 102; Col 3 Ln 56-58);
a source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) on at least one side of the active pattern (FIG 102; Col 3 Ln 56-58);
a lower wiring structure (FIG 2; 216; Col 17 Ln 34-37) on the second surface of the insulating layer (FIG 2; 212; Col 17 Ln 34-38); and
a through-via (FIG 2; 218; Col 4 Ln 39-44) that extending in the insulating layer and connecting the source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) and the lower wiring structure (FIG 2; 216; Col 17 Ln 34-37),
wherein the insulating pattern comprises:
a first portion (FIG 2; 127; Col 6 Ln 54-58) between the insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) and the active pattern (FIG 102; Col 3 Ln 56-58);
Su does not teach
a dummy source/drain pattern extending in at least a portion of the insulating pattern and positioned below the source/drain pattern;
a second portion surrounding at least a portion of the through-via; and
a fourth portion at least partially surrounding the dummy source/drain pattern.
Chen teaches in FIG 2B and FIG 2C a second portion (FIG 2B and FIG 2C; 269 and 229; ¶[0029]¶[0016]) surrounding at least a portion of the through-via (FIG 2B; 358; ¶[0016]); and
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via, and the prior art of Chen, a semiconductor transistor with a dielectric layer surrounds a portion of the through-via. This combination produces a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via with a dielectric layer surrounds a portion of the through-via. The dielectric material surrounding the trough via prevents electrical leakage during electron movement through the transistor Chen(¶[0029]).
Chen does not teach
a dummy source/drain pattern extending in at least a portion of the insulating pattern and positioned below the source/drain pattern;
a fourth portion at least partially surrounding the dummy source/drain pattern.
Lin teaches in FIG 12
a dummy source/drain pattern (FIG 12; 150; ¶[0048]) extending in at least a portion of the insulating pattern (FIG 12; 124; ¶[0048])
a fourth portion (FIG 12; 124; ¶[0048]) at least partially surrounding the dummy source/drain pattern (FIG 12; 150; ¶[0048]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su and Chen, semiconductor devices comprising an insulating layer an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and the prior art of Lin, a semiconductor device with a dummy source/drain sounded by an insulating layer. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern. The purpose of the insulating pattern is to control the isolation of the electrical component in the device Lin[0045].
Lin does not teach positioned below the source/drain pattern
Mukesh teaches in Fig 12 positioned below the source/drain pattern (FIG 12; 124; ¶[0032])
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, Chen and Lin, a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern and the prior art of Mukesh, a semiconductor with a pattern positioned below the source/drain pattern. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain in the position of the placeholder pattern surrounded by an insulating pattern semiconductor. The position of the placeholder pattern with respect to the second surface of the insulating layer determines the methods and procedures used to fabricate the transistors in the semiconductor device to achieve uniformity (Mukesh¶[0032]).
Regarding Claim 16, Su, Chen, Lin and Mukesh teach the semiconductor device of claim 15.
Su does not teach wherein a length of the fourth portion of the insulating pattern in the thickness direction of the insulating layer is greater than a length of the second portion of the insulating pattern in the thickness direction of the insulating layer.
However, the ordinary artisan would have recognized the thickness of the insulation patter to be a result effective variable affecting flow of current in the device. Thus, it would have been obvious to limit the thickness of the insulating patterns within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding Claim 17, Su, Chen, Lin and Mukesh teach the semiconductor device of claim 15.
Su does not teach wherein the second portion of the insulating pattern contacts at least a portion of a side surface of the source/drain pattern.
Chen teaches in FIG 2B and Fig 2C wherein the second portion of the insulating pattern (FIG 2B and FIG 2C; 269 and 229; ¶[0029]¶[0016]) contacts at least a portion of a side surface of the source/drain pattern (FIG 2C; 260; ¶[0016]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via, and the prior art of Chen, a semiconductor device with the second portion of the insulating pattern contacts at least a portion of a side surface of the source/drain pattern. This combination produces a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via wherein the second portion of the insulating pattern contacts at least a portion of a side surface of the source/drain pattern. The dielectric material in contact with the source/drain pattern controls and isolated the electrical components in the device to present leakage Chen(¶[0016]).
Regarding Claim 18, Su, Chen, Lin and Mukesh teach the semiconductor device of claim 15.
Su teaches in FIG 2 wherein a lower surface of the first portion (FIG 2; 127; Col 6 Ln 54-58) of the insulating pattern is farther from the second surface (FIG 2 with annotations; second surface) of the insulating layer than a lower surface of the source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) is from the second surface of the insulating layer (FIG 2 with annotations; second surface).
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Regarding Claim 19, Su teaches in Fig 2 a semiconductor device comprising:
an insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) comprising:
a first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65);
a second surface facing (FIG 2 with annotations; 126; second surface; Col 5 Ln 61-65); and
an element isolation trench (FIG 2; 220; Col 6 Ln 15-19);
an insulating pattern (FIG 2; 127; Col 6 Ln 54-58) on the first surface (FIG 2 with annotations; 126; first surface; Col 5 Ln 61-65) of the insulating layer (FIG 2; 126; Col 5 Ln 61-65);
an active pattern on the insulating pattern and comprising a channel pattern (FIG 102; Col 3 Ln 56-58);
a source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) on at least one side of the active pattern (FIG 102; Col 3 Ln 56-58);
a gate electrode (FIG 2; 104; Col 3 Ln 55) on the insulating pattern and at least partially surrounding the channel pattern (FIG 2; 102; Col 3 Ln 56-58);
a lower wiring structure (FIG 2; 216; Col 17 Ln 34-37) on the second surface of the insulating layer (FIG 2; 212; Col 17 Ln 34-38); and
a through-via (FIG 2; 218; Col 4 Ln 39-44) that extending in the insulating layer and connecting the source/drain pattern (FIG 2; 106, 108 and 120; Col 4 Ln 8-10; Col 5 Ln 17-22) and the lower wiring structure (FIG 2; 216; Col 17 Ln 34-37),
wherein the insulating pattern comprises:
a first portion (FIG 2; 127; Col 6 Ln 54-58) between the insulating layer (FIG 2; 126 and 112; Col 5 Ln 61-65) and the active pattern (FIG 102; Col 3 Ln 56-58);
a third portion (FIG 2; 210; Col 12 Ln 36-40) on a bottom surface of the element isolation trench.
the lower wiring structure (FIG 2; 216; Col 17 Ln 34-37)
Su does not teach
a dummy source/drain pattern extending in at least a portion of the insulating pattern and below the source/drain pattern;
a second portion surrounding at least a portion of the through-via;
a fourth portion at least partially surrounding the dummy source/drain pattern, and wherein the through-via comprises:
a first via portion at least partially surrounded by the second portion of the insulating pattern; and
a second via portion between the first via portion
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Chen teaches in FIG 2B a second portion (FIG 2B; 269; ¶[0029]) surrounding at least a portion of the through-via (FIG 2B; 358; ¶[0016]); and
wherein the through-via comprises:
a first via portion (FIG 2B with annotations; First via portion) at least partially surrounded by the second portion (FIG 2B; 269; ¶[0029]) of the insulating pattern; and
a second via portion (FIG 2B with annotations; Second via portion) between the first via portion (FIG 2B with annotations; First via portion)
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via, and the prior art of Chen, a semiconductor transistor with a dielectric layer surrounds a portion of the through-via and a first via portion at least partially surrounded by the second portion of the insulating pattern and a second via portion between the first via portion. This combination produces a semiconductor transistor device with an insulating layer, insulating pattern, channel structure, source/ drain pattern, lower wiring structure and through via with a dielectric layer surrounds a portion of the through-via with a first via portion at least partially surrounded by the second portion of the insulating pattern and a second via portion between the first via portion. The dielectric material surrounding the trough via prevents electrical leakage during electron movement through the transistor Chen(¶[0029]).
Chen does not teach
a dummy source/drain pattern extending in at least a portion of the insulating pattern and below the source/drain pattern;
a fourth portion at least partially surrounding the dummy source/drain pattern,
Lin teaches in FIG 12
a dummy source/drain pattern (FIG 12; 150; ¶[0048]) extending in at least a portion of the insulating pattern (FIG 12; 124; ¶[0048])
a fourth portion (FIG 12; 124; ¶[0048]) at least partially surrounding the dummy source/drain pattern (FIG 12; 150; ¶[0048]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su and Chen, semiconductor devices comprising an insulating layer an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and the prior art of Lin, a semiconductor device with a dummy source/drain sounded by an insulating layer. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern. The purpose of the insulating pattern is to control the isolation of the electrical component in the device Lin[0045].
Lin does not teach
Below the source drain pattern
Mukesh teaches in Fig 12 positioned below the source/drain pattern (FIG 12; 124; ¶[0032])
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Su, Chen and Lin, a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain sounded by an insulating pattern and the prior art of Mukesh, a semiconductor with a pattern positioned below the source/drain pattern. This combination would produce a semiconductor device comprising an insulating pattern an insulating pattern containing four portions, an active pattern, source/drain pattern, a lower wiring structure and a through-via extending in the insulating layer and a dummy source/drain in the position of the placeholder pattern surrounded by an insulating pattern semiconductor. The position of the placeholder pattern with respect to the second surface of the insulating layer determines the methods and procedures used to fabricate the transistors in the semiconductor device to achieve uniformity (Mukesh¶[0032]).
Regarding Claim 20, Su, Chen, Lin and Mukesh teach the semiconductor device of claim 19.
Su does not teach wherein a length of the second portion of the insulating pattern in the thickness direction of the insulating layer is smaller than a length of the third portion of the insulating pattern in the thickness direction of the insulating layer.
However, the ordinary artisan would have recognized the thickness of the insulation patter to be a result effective variable affecting flow of current in the device. Thus, it would have been obvious to limit the thickness of the insulating patterns within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
Kim(US20230343786A1); This reference teaches a semiconductor device with a dummy source/drain terminal.
Chang(US20230026310A1): This reference teaches a semiconductor device comprising of fins structures over a substrate
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/B.Q.R./ Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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