DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 9, 11, 13, and 16 have been amended.
Claims 1-20 have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2008/0313443 by Terashima (as cited by Applicant and hereinafter referred to as “Terashima”).
Regarding claims 1, 9, and 16, taking claim 1 as representative, Terashima discloses:
a system, comprising: instruction fetch circuitry; decoder circuitry coupled to the instruction fetch circuitry (Terashima discloses, at Figure 1 and related description, fetching instructions, which discloses fetch circuitry, to a decoder, which discloses decoder circuitry coupled thereto.); and
condition aggregation circuitry coupled to the decoder circuitry,…look-up table (LUT) circuitry capable of storing a plurality of combinations of results of first-order condition checks (Terashima discloses, at Figure 1 and related description, a complex condition branching decision unit, which discloses condition aggregation circuitry coupled to the decoder. Terashima also discloses, at Figure 1 and related description, a complex condition setting storage unit, which discloses LUT circuitry capable of storing a plurality of combinations of results of first-order condition checks.);
wherein the instruction fetch circuitry is capable of: fetching a conditional branch instruction from a memory, wherein the conditional branch instruction identifies multiple register locations and a condition aggregation operation, and wherein the condition aggregation operation comprises second-order condition checks (Terashima discloses, at Figure 1 and related description, fetching a complex conditional branch instruction. As disclosed at Figure 4 and related description, the complex conditional branch instruction specifies which comparisons are to be made, which discloses identifying multiple register locations, and a condition for branching, which discloses the aggregating comprises second-order condition checks.); and
providing the conditional branch instruction to the decoder circuitry (Terashima discloses, at Figure 1 and related description, decoding a complex conditional branch instruction.); and
wherein the decoder circuitry is capable of causing the condition aggregation circuitry to perform the second-order condition checks with respect to values stored in the multiple register locations, wherein the values include results of first-order condition checks…and wherein the second-order condition checks are performed in parallel (Terashima discloses, at Figure 4 and related description, the condition for branching involves performing multiple, i.e., second-order, checks with respect to the results of comparisons, which discloses values stored in the multiple register locations. Terashima also discloses, at Figure 3 and related description, parallel comparisons, which discloses the second-order condition checks are performed in parallel.); and
causing the condition aggregation circuitry to provide a result of the second- order condition checks… wherein the result of the second-order condition checks is obtained … based on a combination of the results of the first-order condition checks from the plurality of combinations (Terashima discloses, at Figure 4 and related description, the condition for branching involves performing multiple, i.e., second-order, checks with respect to the results of comparisons, i.e., the results of the first-order condition checks, which discloses providing a result as claimed.).
Terashima does not explicitly disclose that the aforementioned LUT circuitry is included in the aforementioned condition aggregation circuitry. However, Terashima discloses, e.g., in Figure 1, both the complex condition setting storage unit, i.e., the LUT circuitry, and the complex condition branching decision unit, i.e., the condition aggregation unit. Figure 1 shows the two as separate boxes. However, it would have been obvious to show the complex condition setting storage unit as included in the complex condition branching unit. The organization of circuit components is based on well-known design considerations, and locating one component with another component reduces the delays associated with data transmission.
Terashima does not explicitly disclose that the aforementioned first-order condition checks are performed by program control circuitry and the aforementioned providing of the result is to the program control circuitry. However, Terashima discloses program control circuitry, such as conditional branching circuitry. See, e.g., Figure 10A and related description. Both the conditional branching circuitry and the complex conditional circuitry evaluate conditions. It would have been obvious to modify Terashima such that the conditional branching circuitry evaluated the conditions and received the complex condition evaluation results from the complex conditional circuitry. Doing so represents an obvious design choice, e.g., whether to have separate or integrated condition evaluation circuits. A person having ordinary skill in the art would have been motivated to make this modification for any of a number of reasons, such as reducing redundant components, increasing parallelism, and the like.
Terashima does not explicitly disclose the aforementioned result is obtained from the LUT circuitry. However, Terashima discloses storing comparison results in the complex condition setting storage unit. It would have been obvious to store the results in the complex condition setting storage unit to use the results when needed.
Regarding claim 2, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
the condition aggregation circuitry is capable of performing the second-order condition checks with respect to the values stored in the multiple register locations, and wherein the conditional branch instruction comprises an identifier for the condition aggregation operation that defines the second-order condition checks (Terashima discloses, at Figure 4 and related description, the complex conditional branching decision unit performs the second-order condition checks and the complex conditional branch comprises an identifier for the condition checks that are to be performed.).
Regarding claims 3 and 11, taking claim 3 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
input to the LUT circuitry comprises the identifier for the condition aggregation operation and the values from the multiple register locations, and wherein an output from the LUT circuitry comprises the result of the second-order condition checks (Terashima discloses, at Figure 4 and related description, the looking up is performed using the branching value identified by the complex conditional branch instruction and the outputs from the complex condition storage unit.).
Regarding claims 4, 12, and 18, taking claim 4 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
prior to fetching the conditional branch instruction, the instruction fetch circuitry is capable of fetching multiple compare instructions from the memory, wherein the multiple compare instructions identify multiple comparison operations to be performed by arithmetic logic circuitry and wherein the multiple comparison operations comprise the first-order condition checks to be performed …(Terashima discloses, at Figure 5 and related description, processing a number of compare instructions prior to the conditional branch. The comparisons are understood to be performed by arithmetic logic circuitry.).
Terashima does not explicitly disclose that the aforementioned first-order condition checks are to be performed by program control circuitry.
However, Terashima discloses program control circuitry, such as conditional branching circuitry. See, e.g., Figure 10A and related description. Both the conditional branching circuitry and the complex conditional circuitry evaluate conditions. It would have been obvious to modify Terashima such that the complex conditions were evaluated by the conditional branching circuitry. Doing so represents an obvious design choice. A person having ordinary skill in the art would have been motivated to make this modification for any of a number of reasons, such as reducing redundant components, increasing parallelism, and the like.
Regarding claims 5, 13, and 19, taking claim 1 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
…performing the multiple comparison operations (Terashima discloses, at Figure 1 and related description, performing the comparisons.); and
providing comparison results of the multiple comparison operations… (Terashima discloses, at Figure 1 and related description, performing the comparisons, which discloses providing the results.; and
…performing the first-order condition checks with respect to the comparison results, wherein the first-order condition checks are performed in parallel (Terashima discloses, at Figure 1 and related description, determining the results of the comparisons, which discloses performing the first-order condition checks.); and
storing each one of the results of the first-order condition checks in a different one of the multiple register locations (Terashima discloses, at Figure 1 and related description, providing results from the comparisons and storing the results, i.e., in different register locations.).
Terashima does not explicitly disclose that the aforementioned providing the comparison results is to the program control circuitry and the aforementioned performing the checks and storing the results can be performed by performed by the program control circuitry.
However, Terashima discloses program control circuitry, such as conditional branching circuitry. See, e.g., Figure 10A and related description. Both the conditional branching circuitry and the complex conditional circuitry perform comparisons and evaluate conditions. Performing the comparisons is understood to be by arithmetic and logic circuitry that then provides the results. It would have been obvious to modify Terashima such that the conditional branching circuitry evaluated the conditions and received the complex condition evaluation results from the complex conditional circuitry. Doing so represents an obvious design choice, e.g., whether to have separate or integrated condition evaluation circuits. A person having ordinary skill in the art would have been motivated to make this modification for any of a number of reasons, such as reducing redundant components, increasing parallelism, and the like.
Regarding claims 6 and 14, taking claim 6 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
the second-order condition checks comprise a first condition check and a second condition check, and wherein the multiple register locations include a first register location and a second register location (Terashima discloses, at Figure 4 and related description, performing multiple checks for branching using comprarison results, i.e., register locations.).
Regarding claims 7, 15, and 20, taking claim 7 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima also discloses:
the LUT circuitry is capable of: determining if a first result stored in the first register location satisfies the first condition check and a second result stored in the second register location satisfies the second condition check (Terashima discloses, at Figure 4 and related description, performing complex condition checks, such as determining if each of three results are 1, and outputting false if not and true if so, which discloses using first and second results stored in first and second locations.);
outputting a false indication when the first result does not satisfy the first condition check (Terashima discloses, at Figure 4 and related description, performing complex condition checks, such as determining if each of three results are 1, and outputting false if not.);
outputting the false indication when the second result does not satisfy the second condition check (Terashima discloses, at Figure 4 and related description, performing complex condition checks, such as determining if each of three results are 1, and outputting false if not.); and
outputting a true indication when the first result satisfies the first condition check, and the second result satisfies the second condition check (Terashima discloses, at Figure 4 and related description, performing complex condition checks, such as determining if each of three results are 1, and outputting true if so, which discloses using first and second results stored in first and second locations. The number of conditions is arbitrary.).
Claims 8, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Terashima in view of US Patent No. 6,366,999 by Drabenstott et al. (hereinafter referred to as “Drabenstott”).
Regarding claims 8, 10, and 17, taking claim 8 as representative, Terashima discloses the elements of claim 1, as discussed above. Terashima does not explicitly disclose the identifier for the condition aggregation operation comprises a hexadecimal value.
However, in the same field of endeavor (e.g., conditional execution) Drabenstott discloses:
hexadecimal values (Drabenstott discloses, at Table 3, hexadecimal representations in instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Terashima to include hexadecimal representations, as disclosed by Drabenstott, in order to improve efficiency by providing a compact representational format.
Response to Arguments
On page 11 of the response filed September 14, 2026 (“response”), the Applicant argues, “As shown in FIGS. 1 and 2, above, the complex condition storage unit (100, 200, 300, 400), which are part of the complex condition setting storage unit (1) is positioned between the instruction decoder (4) and the condition comparison unit (2). As disclosed by Terashima in FIGS. 1-4 and the related description, the complex condition storage unit (100, 200, 300, 400) performs a comparison of two values, the result of which is provided to the complex condition branching decision unit (3), as shown in FIG. 3. Even assuming arguendo that the complex condition storage unit is comparable to a look-up table (which Applicant does not concede), Terishma does not disclose the complex condition branching decision unit including the complex condition storage unit, let alone disclose that the result of the complex condition branching decision unit is based on the complex condition branching decision unit. In contrast, claim 1 is amended to recite "causing the condition aggregation circuitry to provide a result of the second-order condition checks to the program control circuitry, wherein the result of the second-order condition checks is obtained from the LUT circuitry based on a combination of the results of the first-order condition checks from the plurality of combinations."
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for grounds of rejection of the amended claims. Terashima’s Figure 1 shows the two components in question as separate. The illustration is conceptual, and the distinction drawn between the two components is based on logical function. The illustration does not convey that the two are, or are not, “included” with one another.
For that matter, what does it even mean for one to be included with the other. The Applicant has amended the claim to read that the condition aggregation circuitry includes the LUT circuitry. Does that mean that a physical region on the processor dedicated to the condition aggregation circuitry also includes the separate LUT circuitry? If so, how is the region bound? Or does it mean that the condition aggregation circuitry also performs the function of a LUT? The Applicant has not demonstrated how either case could be in any way related to an inventive concept or have patentable significance.
In any event, including Terashima’s complex condition setting storage unit in the complex condition branching decision unit is merely rearranging the parts. It would have been obvious to do so based on well-known design principles, such as distance versus delay and power distribution.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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