Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 8/24/2026 has been entered. Claims 1, 6-10, and 12-16 remain pending.
Applicant’s amendments have overcome the objections to claims 7 and 13. Thus, Examiner is withdrawing the objections to Claims 7 and 13.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant first traverses the 102 rejections. Applicant states that the traversal is based on the rejection of the originally presented claims (See first paragraph of pg. 6 of Applicant’s response). However, Applicant then appears to be arguing that the prior art references do not teach every limitation of the amended claims.
Examiner agrees that no prior art reference in the original Office Action teaches every limitation of the amended claims. However, the amended claims are very similar to the originally presented claims. For example, Claim 1 is largely the same as originally presented Claim 5, which was rejected under 103.
Applicant traverses the 103 rejection of Claim 5 (for example) on the ground that the collective teachings of the cited prior art references do not disclose or suggest all the limitations of this (and other claims), and there is no motivation to modify the references to reach the stated limitations.
In the Non-Final Office Action, Examiner rejected claim 5, for example, and cited the teachings of the prior art that read on the limitations, as well as the motivation to combine the prior art references. In Claim 5, Examiner acknowledged that Huang in view of Lin does not disclose that the interconnect of Huang is a power delivery network. Examiner then cited Chiang for teaching of a backside power rail, and cited Chiang to provide a motivation to add it to the structure disclosed by Huang in view of Lin (“As disclosed by Chiang, adding a backside power rail increases the number of metal tracks available in the device for directly connecting to the source/drain contact features and via features….”).
Since Applicant did not contest this motivation in the traversal, and amended Claim 1 is largely the same subjection matter as originally presented Claim 5, Examiner is largely applying the rejection of originally presented Claim 5 to amended Claim 1. The same applies to the other 103 rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16, and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable US20230197815A1 (Huang) in view of US20230369456A1 (Lin) and US20210305252A1 (Chiang).
Regarding Claims 1 and 16, Huang discloses an integrated circuit (Fig. 1A, Para. [0029]) comprising a semiconductor structure (Fig. 2F, Para. [0042]), comprising: a first frontside source/drain region (Fig. 2F, el. 107, Para. [0044]); a dielectric isolation layer (Fig. 2f, el. 105, Para. [0044]) disposed on a bottom surface of the first frontside source/drain region (Fig. 2f); a first frontside source/drain metal contact (Fig. 2f, el. 109, Para. [0044]) disposed on a top surface and over a portion of each sidewall of the first frontside source/drain region (Fig. 2F). a backside middle-of-the line contact (Fig. 2F, el. 113, Para. [0044]) disposed in the backside interlayer dielectric layer (Fig. 2F) and on a bottom surface of the first frontside source/drain metal contact (Huang, Fig. 2F, Para. [0044]), wherein the backside middle-of-the-line contact connects the first frontside source/drain metal contact to a backside interconnect (Fig. 1A, el. 115, Para. [0030]).
Huang does not disclose a sidewall spacer disposed on a remaining portion of each sidewall of the first frontside source/drain region, does not disclose that the first frontside source/drain metal contact is further disposed on at least one sidewall of the sidewall spacer and extends into a backside interlayer dielectric layer, and does not disclose that the backside middle-of-the-line contact connects the first frontside source/drain metal contact to a backside power delivery network.
Lin discloses a semiconductor structure (Fig. 1A, Para. [0021]) with spacers (Fig. 1A, el. 104, Para. [0022]) around source/drain regions (Fig. 1A, el. 102B1, Para. [0022]).
Chiang discloses a semiconductor structure (Figs. 25B, Para. [0086) comprising a source/drain region (Fig. 25B, el. 260, Para. [0078]), a contact (Fig. 25B, el. 384, Para. [0078]), and a backside power rail (Fig. 25B, el. 390, Para. [0078]), wherein the source/drain region is connected to the backside power rail through the contact (Fig. 25B, Para. [0078]).
First, it would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add spacers to the S/D region in Huang, as disclosed by Lin. As disclosed by Lin, this has the benefit of limiting the epitaxial lateral growth of each side of the S/D region (Para. [0018]).Also, when spacers are added, the metal contact 109 in Fig. 2F of Huang will be disposed on a sidewall of the added spacer.
Second, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to separate the dielectric layer 105 in Fig. 2F of Huang into a dielectric isolation layer and a backside interlayer dielectric layer. This is an example of making parts separable (MPEP 2144.04 (V)(C)). Also, note that these layers, per Applicant’s specification, can be made of the same material (Para. [0056] and Para. [0072]), which provides further evidence that it would be obvious to consider a single layer as two layers.
Finally, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add the backside power rail, as disclosed by Chiang, to the device of Huang in view of Lin. As disclose by Chaing, adding a backside power rail increases the number of metal tracks available in the device for directly connecting to source/drain contact features and via features, while increasing gate density for greater device integration compared to structures without the backside power rails (Para. [0094]).
Regarding Claim 6, Huang in view of Lin and Chiang discloses the semiconductor structure according to claim 1, further comprising a frontside back-end-of-the-line interconnect disposed over a top surface of the first frontside source/drain metal contact (Huang, Fig. 1a, el. 111, Para. [0031]).
Regarding Claim 7, Huang in view of Lin and Chiang discloses the semiconductor structure according to claim 1, further comprising a second frontside source/drain region adjacent to the first frontside source/drain region (Huang, see Fig. 1A, which discloses two adjacent source/drain regions 107).
Regarding Claim 8, Huang in view of Lin and Chiang discloses the semiconductor structure according to claim 7, further comprising a second frontside source/drain metal contact disposed on the second frontside source/drain region (Huang, see Fig. 1A, where both source/drain regions 107 have metal contacts 109 above them).
Regarding Claim 9, Huang in view of Lin and Chiang discloses the semiconductor structure according to claim 8, wherein the second frontside source/drain metal contact connects the second frontside source/drain region to a frontside back-end-of-the-line interconnect (Fig. 1a, el. 111, Para. [0031]).
Claims 10 and 13-14 is rejected under 35 U.S.C. 103 as being unpatentable over US20190165118A1 (Leobandung) in view of Chiang.
Regarding Claim 10, Leobandung discloses a semiconductor structure (Figs. 1A-1D, el. 100, Para. [0033]), comprising: a first frontside source/drain metal contact (Fig. 1D, el. 190, Para. [0040]); and a first frontside source/drain region (Fig. 1D, el. 170, Para. [0040]) fully disposed within the first frontside source/drain metal contact (Fig. 1D, Para. [0040]).
Leobandung does not disclose that a bottom surface of the first frontside source/drain metal contact is connected to a backside power delivery network.
Chiang discloses a semiconductor structure (Figs. 25B, Para. [0086) comprising a source/drain region (Fig. 25B, el. 260, Para. [0078]), a contact (Fig. 25B, el. 384, Para. [0078]), and a backside power rail (Fig. 25B, el. 390, Para. [0078]), wherein the source/drain region is connected to the backside power rail through the contact (Fig. 25B, Para. [0078]).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add the backside power rail, as disclosed by Chiang, to the device of Leobandung. As disclose by Chaing, adding a backside power rail increases the number of metal tracks available in the device for directly connecting to source/drain contact features and via features, while increasing gate density for greater device integration compared to structures without the backside power rails (Para. [0094]).
Regarding Claim 13, Leobandung in view of Chiang discloses the semiconductor structure according to claim 10, further comprising a second frontside source/drain region adjacent to the first frontside source/drain region (Leobandung, Fig. 1A, el. 172, Para. [0034]).
Regarding Claim 14, Leobandung in view of Chaing discloses the semiconductor structure according to claim 13, further comprising a second frontside source/drain metail contact disposed on the second frontside source/drain region (Leobandung, Fig. 1A, el. 192, Para. [0039]).
Claim 12 is rejected under 35 U.S.C. 103 as obvious over Leobandung in view of Chiang and Huang.
Regarding Claim 12, Leobandung in view of Chiang discloses the semiconductor structure according to claim 11.
Leobandung in view of Chiang does not disclose a frontside back-end-of-the-line interconnect disposed over a top surface of the first frontside source/drain metal contact.
Huang discloses a semiconductor structure with a frontside back-end-of-the line interconnect disposed over a top surface of a first frontside source/drain metal contact (see analysis of claim 6 above).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a frontside back-end-of-the line interconnect disposed over a top surface of the source/drain region to Leobandung in view of Chiang. As disclosed by Huang, this has the benefit of allowing connection to other parts of the circuit (Para. [0031]).
Claim 15 is rejected under 35 U.S.C. 103 as obvious over Leobandung in view of Chaing and Huang Huang.
Regarding Claim 15, Leobandung in view of Chaing discloses the semiconductor structure according to claim 14.
Leobandung in view of Chaing does not disclose that the second frontside source/drain metal contact connects the second frontside source/drain region to a frontside back-end-of-the-line interconnect.
Huang discloses a semiconductor structure with a frontside back-end-of-the line interconnect disposed over a top surface of a first frontside source/drain metal contact (see analysis of claim 6 above).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a frontside back-end-of-the line interconnect disposed over a top surface of the source/drain region to Leobandung . As disclosed by Huang, this has the benefit of allowing connection to other parts of the circuit (Para. [0031]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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