DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12, in the reply filed on July 21st, 2026 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected groups, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 21st, 2026.
Claim Interpretation
Regarding claim 1, the phrase “for manufacturing a component carrier” is considered an intended use type phrase, wherein a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Therefore, will be considered met if the prior art sheet is used in the process of making or forms part of a component carrier, wherein the term “component carrier” will be interpreted as set forth in the specification as any support structure which is able to accommodate one or more components thereon [PGPub, 0010], which will be considered any structure able to support more than its own weight, which can be implied or explicit.
Regarding claim 9, the phases “is configured for exposure to chemical and/or mechanical processing” and “is configured for being laminated on a base structure” will be interpreted as “adapted to/configured for” type phrases, wherein it has been held that the recitation that an element is “adapted to” perform a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Hutchinson, 69 USPQ 138.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 & 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gong et al. (CN 110202876 A) (hereinafter “Gong”).
Regarding claims 1-3 and 12, Gong teaches a bendable board (sheet) usable as a support [0004] comprising a first sheet/layer (structure) comprising curable epoxy (resin matrix) and a first (solid) inorganic filler, such as silicon dioxide [0012-0014] and the second sheet/layer (structure) comprises a second inorganic filler comprising hollow glass microspheres (or porous silica) [0015-0018], wherein the amount of air in a hollow inorganic filler is inherently larger than that of a solid inorganic filler.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Gong, as applied to claim 1 above.
Regarding claims 10-11, the first and second semi-cured sheets are stacked and hot pressed [0028], wherein depending on the cure level and pressure/heat applied an interface plane or an intermingled interface may result, wherein the interface structure would have been well understood and selected by one of ordinary skill in the art.
Claims 1-3 & 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (KR 20200041094 A) (hereinafter “Park”).
Regarding claims 1-3 and 12, Park teaches a shielding film (sheet) for mounting a printed circuit board [0112], wherein a first conductive layer (second structure) (All Figs. [20]) comprises hollow conductive particles (All Figs. [21]) dispersed in a resin and a second conductive layer (first structure) (All Figs. [30]) comprises non-hollow conductive particles (All Figs. [31]) dispersed in a resin [0011], wherein the amount of air in a hollow inorganic filler is inherently larger than that of a solid inorganic filler.
Claims 4-5 & 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Park, as applied to claims 1 & 3 above.
Regarding claims 4-5 and 9, the hollow conductive particles comprise an average particle size of 1 to 30 µm [0015] and the hollow conductive particles comprise an average particle size of 5 to 20 µm, and the thickness of the first conductive layer is 10 to 40 µm before pressurization and the thickness of the second conductive layer at any stage is 10 to 30 µm, wherein although Park’s ranges do not anticipate Applicant’s, where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). MPEP 2144.05 I.
Regarding claims 10-11, the first and second semi-cured layers are stacked and hot pressed [0191-0192], wherein depending on the cure level and pressure/heat applied an interface plane or an intermingled interface may result, wherein the interface structure would have been well understood and selected by one of ordinary skill in the art.
Claims 1-5, 9, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (JP 2008-302677 A) (hereinafter “Goto”) in view of Shigaki et al. (WO 2019/230661 A1) (hereinafter “ShigakI”), and optionally Ohmi et al. (U.S. Pub. No. 2009/0120673 A1) (hereinafter “Ohmi”) and Kaimori (U.S. Pub. No. 2019/0215957 A1) (hereinafter “Kaimori”).
Regarding claims 1-5, 9, and 12, Goto teaches a multilayer insulating film for manufacturing an insulating build-up layer on a core substrate (base structure) for usable as a packaging mount [0030] comprising a first layer comprising resin and inorganic filler with an average particle size of 0.01 to 2 µm and a second layer comprising resin and inorganic filler having a larger average particle size than the first layer in the range of 0.1 to 10 µm [0010-0011], wherein the first layer due to the relatively smaller particle size is configured to provide a smooth surface comprising a low roughness (Ra) of 200 nm or less after chemical treatment, preferable as a plating surface [0004, 0011, 0027] and the second layer due to the relatively larger particle size configured to absorb irregularities and differences in height/gaps, such as due a circuit pattern, when laminated to the core substrate [0003, 0011, 0030], wherein silica is preferably as the inorganic filler [0022] which can be in hollow (silica balloons) form [0020], wherein and an example provides solid silica filler in a first layer having a diameter of 0.2 µm and solid silica filler in a second layer having a diameter of 0.3 µm [0022, 0034, 0037].
However, the use of (hollow) silica balloons is not motivated for the first layer (and second layer).
Shigaki teaches an insulation layer for a package laminate [0002, 0073], wherein the requirements are low water absorption, low dielectric constant, low dielectric loss tangent, and low thermal expansion coefficient, wherein further reducing dielectric constant is in high demand [0002, 0006], wherein the air inside the cavity contained inside the provides the most significant effect in reducing the dielectric constant [0011, 0058], wherein the hollow particles with small particle sizes one can improve both appearance and insulation properties when making resin sheets, wherein the hollow particle comprise a size in the range of 0.01 to 10 µm, wherein a lower limit of the average particle diameter is preferably 0.1 µm or more and an upper limit is preferably 8 µm, more preferably 0.3 µm or more to 6 µm or less, and most preferably 0.4 µm or more and 4 µm or less [0059], wherein the dielectric constant (Dk) and dielectric loss tangent (Df) were significantly lower using hollow silica rather than solid silica at the same volume amount [0090, 0095, 0102].
It would have been obvious to one of ordinary skill in the art at the time of invention to provide the second layer having the larger particle size, and optionally also the first layer, with hollow filler particles, replacing the solid particles. One of ordinary skill in the art would have been motivated to provide an improved dielectric constant (Dk) and dielectric loss tangent (Df) in high demand by replacing solid particles, wherein the larger particles of the second layer would contain the larger amount of air/vacuum for a greater effect (than the solid particles and also hollow particles having a smaller diameter).
Further regarding claims 1-3, in the event the amount of hollow volume/air in the second filler is not greater than that of the first filler comprising solid particles is not taught:
Ohmi teaches an insulating film for a multilayer board for mounting an electronic device thereon [0001-0003], wherein the inclusion of porous particles can cause a large number of irregularities, wherein the insulating film comprises a lower/second porous insulating layer (All Figs. [1a]) comprising hollow (silica) particles embedded in a resin matrix [0003, 0043, 0059] and a first/upper non-porous insulating layer not including any porous materials for a low roughness and comprises a thickness lower than the porous layer in order to provide the necessary permittivity [0009-0010, 0045-0048] but also greater than the diameter of the porous particles to minimize any irregularities [0048], but it is not clear if the non-porous layer includes solid particles.
Kaimori teaches an insulating layer for use in manufacturing substrates comprising a surface layer having a low roughness adjacent the attached circuit/metal layer, wherein the upper/first layer has no filler or a lower content of filler than the second layer [0086-0087, Fig. 4], wherein preferably at least some filler is contained to [0023] to suppress permittivity from being changed due to temperature fluctuations (improved thermal expansion coefficient properties) [0052-0055, 0077], wherein the filler size is 0.1 and 10 µm, preferably 0.5 to 5 µm [0051-0055], wherein solid silica is preferably the inorganic filler in order to suppress linear expansion coefficient [0055].
It would have been obvious to one of ordinary skill in the art at the time of invention to replace only the solid filler particles in the second layer with hollow filler particles and wherein the first layer remain solid filler particles, such that the hollow volume/air contained within the first solid filler particle would be inherently smaller than that of the second hollow filler particle. One of ordinary skill in the art would have been motivated to provide improved roughness by not including hollow filler particles at all in a low roughness surface layer [Ohmi], wherein the treated surface layer would contain at least some solid filler particles such that the thermal expansion coefficient effects do not affect the permittivity under temperature fluctuations [Kaimori].
Claims 1-2, 6-9, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (JP 2008-302677 A) (hereinafter “Goto”) in view of Shigaki et al. (WO 2019/230661 A1) (hereinafter “ShigakI”), and optionally Sakauchi et al. (U.S. Pub. No. 2020/0231786 A1) and/or Liu et al. (CN 103249286 A) (hereinafter “Liu”).
Regarding claims 1-2, 6-9, and 12, Goto teaches a multilayer insulating film for manufacturing an insulating build-up layer on a core substrate (base structure) for usable as a packaging mount [0030] comprising a first layer comprising resin and inorganic filler with an average particle size of 0.01 to 2 µm and a second layer comprising resin and inorganic filler having a larger average particle size than the first layer in the range of 0.1 to 10 µm [0010-0011], wherein the first layer due to the relatively smaller particle size is configured to provide a smooth surface comprising a low roughness (Ra) of 200 nm or less after chemical treatment, preferable as a plating surface [0004, 0011, 0027] and the second layer due to the relatively larger particle size configured to absorb irregularities and differences in height/gaps, such as due a circuit pattern, when laminated to the core substrate [0003, 0011, 0030], wherein silica is preferably as the inorganic filler [0022] which can be in hollow (silica balloons) form [0020], wherein and an example provides solid silica filler in a first layer having a diameter of 0.2 µm and solid silica filler in a second layer having a diameter of 0.3 µm [0022, 0034, 0037].
However, the use of (hollow) silica balloons is not motivated for the first layer (and second layer).
Shigaki teaches an insulation layer for a package laminate [0002, 0073], wherein the requirements are low water absorption, low dielectric constant, low dielectric loss tangent, and low thermal expansion coefficient, wherein further reducing dielectric constant is in high demand [0002, 0006], wherein the air inside the cavity contained inside the provides the most significant effect in reducing the dielectric constant [0011, 0058], wherein the hollow particles with small particle sizes one can improve both appearance and insulation properties when making resin sheets, wherein the hollow particle comprise a size in the range of 0.01 to 10 µm, wherein a lower limit of the average particle diameter is preferably 0.1 µm or more and an upper limit is preferably 8 µm, more preferably 0.3 µm or more to 6 µm or less, and most preferably 0.4 µm or more and 4 µm or less [0059], wherein the dielectric constant (Dk) and dielectric loss tangent (Df) were significantly lower using hollow silica rather than solid silica at the same volume amount [0090, 0095, 0102].
It would have been obvious to one of ordinary skill in the art at the time of invention to provide the second layer having the larger particle size, and optionally also the first layer, with hollow filler particles, replacing the solid particles. One of ordinary skill in the art would have been motivated to provide an improved dielectric constant (Dk) and dielectric loss tangent (Df) in high demand by replacing solid particles, wherein the larger particles of the second layer would contain the larger amount of air/vacuum for a greater effect (than the solid particles and also hollow particles having a smaller diameter).
Further regarding claims 1-2 and 6, in the event the amount of hollow volume/air in the second filler is not greater than that of the first filler (also containing air) is not considered taught:
Sakaughi teaches an insulating layer for use in a semiconductor chip package/wiring board [0243] having a low dielectric loss tangent [0220-0221], wherein the surface is ground using chemical treatment to provide an intended surface roughness (Ra) of preferably 500 nm or less, preferably 100 nm or less [0224, 0241], wherein small particles are provided adjacent the surface so as not to form recesses [0216-0217, Fig. 3], the inorganic filler which includes hollow filler particles has an average particle diameter of preferably 0.5 µm or more and 20 µm or less, especially preferably 5 µm or less, with a maximum particle diameter more preferably less than 10 µm, wherein the enclosed cavity of the hollow filler adjacent the surface should be minimized such as to not form large recesses following chemical treatment [0174-0175, 0178, 0180, 0218-0219, Fig. 4].
AND/OR
Liu teaches a first and second resin embedded hollow microsphere layers, wherein the second hollow microsphere in the second layer has a larger particle size than the first hollow microsphere in the first layer, such that a gradient dielectric constant can be obtained, which improves an absorption of electromagnetic energy [0020, 0038, 0097].
It would have been obvious to one of ordinary skill in the art at the time of invention to replace the solid filler particles of both the first and second layers with hollow filler particles, wherein both the size of the first hollow filler particle the hollow volume/air contained is smaller than that of the second hollow filler particle. One of ordinary skill in the art would have been motivated to provide the smallest internal pore size particles in a layer adjacent the a surface intended to have a low roughness for a decreased potential for recesses formed by hollow filler particles adjacent the treated surface [Sakaughi] and/or to provide a gradient in dielectric constant to increase electromagnetic wave absorption [Liu].
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Goto in view of Shigaki, and optionally Ohmi/Kaimori OR Sakauchi and/or Liu, as applied to claim 1, further in view of Yokota et al. (U.S. Pub. No. 2013/0108861 A1) (hereinafter “Yakota”).
Regarding claims 10-11, Goto teaches that the layers are laminated, but does not teach any particulars regarding cure state and/or lamination specifications [0028].
Yokota teaches an improvement on the process of Goto [0004-0005] such that only one type of resin is used [0008],wherein the insulation layer comprises a first film having a relatively smaller particle size and a second film having a relatively larger particle size, wherein the films are B-staged/semi-cured before lamination and pressing [0100-0102, 0106-0107], wherein the characteristics of the lamination can be such that an interface plane is formed between a first region containing only the first particles and a second region containing only second particles, but allows for intermingling between the particles at a contact interface thereof [0013, 0028-0030].
It would have been obvious to one of ordinary skill in the art at the time of invention to provide an improved/specified process that allows for the formation of an interface plane or some intermingling at an interface formed by hot pressing B-staged/semi-cured films. One of ordinary skill in the art would have been motivated to provide same multilayer effects of a low roughness surface and conformability while providing the same resin to both layers.
Claims 1-3, 9, & 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ando et al. (U.S. Pub. No. 2024/0206061 A1) (hereinafter “Ando”).
Regarding claims 1-3, 9, and 12, Ando teaches an insulation layer for manufacturing a wiring substrate for the mounting of a multi-terminal component [0016], which is also taught by JP 2006-45388 [‘388; 0002-0004] incorporated by reference [0003], wherein the insulating layer comprises a two-layer structure having a first/lower layer (second component) (All Figs. [4a]) and a second/upper layer (first component) (All Figs. [4b]), wherein the second/upper layer is configured for chemical roughening treatment to provide a predetermined low surface roughness of 0.15 µm (150 nm) or less without deep recesses being formed [0025-0027] for the plating of additional metal layers [0026-0027] and the first/lower layer is configured for lamination to a core layer or previously disposed insulation layers (All Figs. [4]) having conductor patterns (All Figs. [3]) [Fig. 1], wherein the first/lower layer comprises a first inorganic filler particles comprising a relatively larger particle size than that the second/upper layer [0037], wherein the first inorganic filler particles may be hollow filler particles in replacement of the solid filler particles to further reduce the dielectric constant [0035], wherein the first/lower layer can be about 90% or more the thickness of the insulating layer, wherein using an exemplary insulation layer thickness of 30 µm, a thickness of the first/lower layer can be 27 µm or higher and a second/upper layer can be 1 to 3 µm [0022-0023], wherein according to ‘388 the second/upper layer A/X is intended to provide a low roughness surface during plating [0026] and the first/lower layer B/Y is intended to fill gaps in circuit patterns and create adhesion to circuitry located on the adherend [0087, 0103, 0107-0109].
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ando, as applied to claim 3 above.
Regarding claims 4-5, Ando further teaches the particle size of the relatively larger first inorganic (hollow) particle is about 0.3 µm to 3 µm and the particle size of the second inorganic filler particles are about 0.1 µm to 1 µm [0022-0023], such that the claimed ranges are prima facie obvious.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ando, as applied to claim 3 above, in view of Sakauchi et al. (U.S. Pub. No. 2020/0231786 A1) and/or Liu et al. (CN 103249286 A) (hereinafter “Liu”).
Regarding claims 6-8, Ando further teaches the particle size of the larger first inorganic (hollow) particle is about 0.3 µm to 3 µm and the particle size of the second inorganic filler particles are about 0.1 µm to 1 µm [0022-0023], such that the claimed ranges are prima facie obvious.
However, the first relatively smaller particle is not taught to also be hollow, wherein a volume or air contained therein being lower than the relatively larger hollow particle.
Sakaughi teaches an insulating layer for use in a semiconductor chip package/wiring board [0243] having a low dielectric loss tangent [0220-0221], wherein the surface is ground using chemical treatment to provide an intended surface roughness (Ra) of preferably 500 nm or less, preferably 100 nm or less [0224, 0241], wherein small particles are provided adjacent the surface so as not to form recesses [0216-0217, Fig. 3], the inorganic filler which includes hollow filler particles has an average particle diameter of preferably 0.5 µm or more and 20 µm or less, especially preferably 5 µm or less, with a maximum particle diameter more preferably less than 10 µm, wherein the enclosed cavity of the hollow filler adjacent the surface should be minimized such as to not form large recesses following chemical treatment [0174-0175, 0178, 0180, 0218-0219, Fig. 4].
AND/OR
Liu teaches a first and second resin embedded hollow microsphere layers, wherein the second hollow microsphere in the second layer has a larger particle size than the first hollow microsphere in the first layer, such that a gradient dielectric constant can be obtained, which improves an absorption of electromagnetic energy [0020, 0038, 0097].
It would have been obvious to one of ordinary skill in the art at the time of invention to replace the solid filler particles of both the first and second layers with hollow filler particles, wherein both the size of the first hollow filler particle the hollow volume/air contained is smaller than that of the second hollow filler particle. One of ordinary skill in the art would have been motivated to provide decreased potential for recesses formed by hollow filler particles adjacent the treated surface [Sakaughi] and/or to provide a gradient in dielectric constant to increase electromagnetic wave absorption [Liu].
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ando, as applied to claim 1, alone or optionally further in view of Yokota et al. (U.S. Pub. No. 2013/0108861 A1) (hereinafter “Yakota”).
Regarding claims 10-11, ‘388, incorporated by reference by Ando [0003], teaches that the first/upper layer A and second/lower layer B of a multilayer insulating layer structure are laminated and heat-pressed in a semi-cured state [0070, 0082, 0091, 0101, 0109, 0112], wherein depending on the cure level and pressure/heat applied an interface plane or an intermingled interface may result, wherein the interface structure would have been well understood and selected by one of ordinary skill in the art.
Yokota teaches a multilayer insulation layer comprising a first film having a relatively smaller particle size and a second film having a relatively larger particle size, wherein the films are B-staged/semi-cured before lamination and pressing [0100-0102, 0106-0107], wherein the characteristics of the lamination can be such that an interface plane is formed between a first region containing only the first particles and a second region containing only second particles, but allows for intermingling between the particles at a contact interface thereof [0013, 0028-0030].
It would have been obvious to one of ordinary skill in the art at the time of invention to provide an improved/specified process that allows for the formation of an interface plane or some intermingling at an interface formed by hot pressing B-staged/semi-cured films. One of ordinary skill in the art would have been motivated to provide same multilayer effects of a low roughness surface and conformability while providing the same/similar resin to both layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Uenishi et al. (JP 2012-211269 A) teach a substantially similar invention to Yokota also improving on, but rather than the fillers being substantially localized to their regions via matching the melting temperatures of the resin and curing agent, the fillers are substantially localized to a first region (R1) and third region (R3) via uneven distribution in the stacked layers prior to lamination and pressing, wherein the second region (R2) disposed therebetween comprises either an interface plane or an intermingled region containing both fillers.
Ikemoto et al. (U.S. Pub. No. 2023/0345624 A1), similar to and corroborating Liu, teach a multilayer substrate comprising either a gradient density or gradient in void size, wherein in a relationship where density decreases or void size increases along a thickness direction away from the outer region of the surface, which provides the side adjacent the added outer metal layer with additional strength and also improves dielectric constant and loss [0159-0162, Fig. 30].
Lee et al. (U.S. Pub. No. 2014/0065413 A1) teach a multilayer insulation film that provides a reinforced surface intended to prevent recesses/dents during processing of circuit/wiring layers [0012-0015, 0043], wherein a first/upper layer is a reinforcing layer comprising resin and filler [0044], such as silica, wherein an exemplary reinforcing layer comprises a thickness of about 2 to 4 µm and a filler size of about 1 to 3 µm [0073], and the second/lower layer comprises a more typical insulating layer comprising resin and filler [0042].
Yamada et al. (JP 2017-055069 A) teaches a multilayer insulation film that rather than decreasing the amount of filler in the surface closest to the surface as is the conventional wisdom, which causes an unnecessary increase in thermal expansion coefficient [0007], rather increases the concentration of the layer closest to the surface relative to the layer therebelow [0008-0010, 0027], wherein while hollow glass beads can are an option, fused silica is preferred due to a low thermal expansion and high fluidity when filled into the resin [0023], wherein an average particle size is preferably 0.01 to 3 µm, most preferably 0.1 to 1 µm in terms of surface roughness, wherein an example comprise a first and second layer comprising the same resin and filler size (SC-2050-KNK has a filler size of 0.5 µm evidenced by JP 2017-193693 [0149]) but different in concentration, that were stacked and cured on a PET film a surface roughness (Ra) of 0.11 µm (110 nm) and a relatively low CTE, while comparative example 1 comprising a lower loading may have an equivalent surface roughness of 0.10 µm (100 nm), a substantial increase in thermal expansion coefficient is also imparted, and when comparative example 2 increases the filler content to an amount equivalent to the average of the multilayer insulation film while the CTE is lowered, the surface roughness is more than doubled [Table 2, 0047-0056].
Osawa et al. (CN 10423530 A) teach a multilayer printed board intended to function as a component mount [0004, 0076-0077], wherein the one or more build-up layers are formed from insulation films contain filler particles, such as silica, hollow silica, alumina, and talc, wherein a filler size is preferably 20 nm to 1 µm in order to prevent roughness [0069].
One of ordinary skill in the art could imagine modifying any of the above three references similar to Goto as recited above and/or modifying them in view of Ando.
Lastly, while Fujishima (JP 2024085325 A) does not contain a publishing date relevant for the U.S., its Japanese filing date predates that of Applicant and has also been filed in China (CN 118185428 A) where its Chinese filing date is after that of the current application.
Fujishima teaches a resin composition layer for circuit board and semiconductor chip mounting comprising a multilayer insulating layer comprising a first/lower composition layer (All Figs. [110]) comprising resin and a first inorganic filler comprising a hollow inorganic filler resulting in a low dielectric constant and permittivity [0005, 0020, 0055-0056] and a second composition layer (All Figs. [120]) having a small surface roughness after roughening comprising a second resin and a second inorganic filler that does not contain a hollow component [0016, 0022-0025], wherein the first inorganic hollow filler comprises a particle size preferably 0.1 µm or more and 10 µm or less, most preferably 0.3 µm or more and 3 µm or less [0064], wherein the particle size of the second inorganic solid filler may be smaller, larger, or the same size as the hollow inorganic filler, preferably in the range of 0.01 µm or more and 5 µm or less, most preferably 0.3 µm or more and 1 µm or less [0077].
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to JEFFREY A VONCH whose telephone number is (571)270-1134. The Examiner can normally be reached M-F 9:30-6:00.
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Frank J Vineis can be reached at (571)270-1547. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEFFREY A VONCH/Primary Examiner, Art Unit 1781 October 13th, 2026
