DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/15/2026 have been fully considered but they are not persuasive. Regarding claim 1, applicant argues that Kaneko does not disclose an intermediate layer disposed between the bonding component (6) and the second metal layer (72) since the “flux” discussed in paragraph 88 is subsequently removed. Flux helps adhere solder to the metal layer during reflow and reduces oxidation of the metal. After bonding, excess flux is cleaned or removed after bonding. Kaneko describes the flux o be applied to pad P2 and the solder ball to be mounted thereon, followed by fixing the solder ball by reflow, and cleaning the surface to remove flux. This would not be the metal surface being cleaned since the solder ball has already been mounted. Even if the flux were removed after mounting, this intermediate step reads on the claimed invention. Applicant’s specification describes an embodiment that uses an intermediate layer to protect the device by preventing cracking, which can also have surface roughness, but the claims to not further differentiate this layer over the prior art’s use of flux. Regarding claim 17, applicant argues that the providing and removing dielectric step to expose the metal layers does not occur after forming the encapsulation to surround the electronic units. However, reference Lin does show encapsulating (170) and forming a dielectric (178) prior to exposing a metal layer (110). Lin is not relied upon to describe the order or number of surface treatments on the metal layers, only that encapsulating multiple units would have been obvious. Additionally, one would be motivated to encapsulate prior to subsequent processing steps since Lin describes that the encapsulant protects the device from external element and contaminants, which would include contaminants during subsequent grinding and CMP operations (paragraphs 62-63).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (US Publication No. 2015/0008020) in view of Mun et al. (US Publication No. 2022/0068822).
Regarding claim 1, Kaneko discloses an electronic device, comprising:
an electronic unit (3)
a circuit structure (1) electrically connected to the electronic unit (3) and comprising (Figure 2):
a first metal layer (52) electrically connected to the electronic unit (3)
a first dielectric layer (82/60) disposed on the first metal layer (52) and having an opening (P2)
a second metal layer (72) disposed in the opening (P2)
a bonding component (6) overlapping the second metal layer (72) and at least partially disposed in the opening (P2)
an intermediate layer (flux) disposed between the bonding component (6) and the second metal layer (72) (paragraph 88)
wherein in a cross-sectional view of the electronic device (Figure 1), a vertical distance between a top surface of the first dielectric layer (82/60) and a top surface of the first metal layer (52) along a normal direction of the electronic device is a first height, another vertical distance along the normal direction between a top surface of the second metal layer (72) and the top surface of the first metal layer (52) is a second height, the first height (82X) is greater than the second height (P2)
Kaneko does not clearly disclose an encapsulation layer surrounding the electronic unit. However, Mun discloses an encapsulation layer (230) surrounding an electronic unit (220). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date to have modified the electronic device of Kaneko to include an encapsulation layer surrounding the electronic unit, as taught by Mun, since it can improve adhesion in vertical connections, rigidity of the device, and heat dissipation (paragraphs 3 and 46).
Kaneko is silent regarding a difference between the first height and the second height is greater than or equal to 1 μm and less than or equal to 15 μm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kaneko’s height difference to be within this range to optimize device thickness against adhesion and alignment of the external connection, thereby improving reliability of the connection (paragraph 96), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 2, Kaneko discloses the second metal layer (72) has a recessed (82X) top surface.
Regarding claim 3, Mun discloses the encapsulation layer further comprises filling particles (paragraph 27). Mun is silent regarding a particle size of the filling particles is greater than or equal to 0.1 μm and less than or equal to 50 μm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the particles size to be within this range to balance delamination and rigidity of the structure (paragraph 27), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Kaneko discloses intermediate layer is disposed in an opening (P2) of the first dielectric layer (paragraph 88).
Regarding claim 7, Kaneko discloses the intermediate layer (flux) is directly contacted with a part of the bonding component (6) and a part of the second metal layer (72) in the opening (paragraph 102).
Regarding claim 8, Kaneko discloses the top surface of the second metal layer (72) is a rough surface (P2).
Regarding claim 9, Kaneko discloses roughness of the top surface of the second metal layer (72) is greater than or equal to 0.2 μm and less than or equal to 5 μm (paragraph 79).
Regarding claim 10, Kaneko discloses the electronic unit comprises: a chip (3); a first insulating layer (5) disposed on the chip (3); and a second insulating layer (81) disposed on the first insulating layer (5), wherein, a thickness of the first insulating layer (5) along the normal direction is smaller than a thickness of the second insulating layer (81).
Regarding claim 11, Kaneko discloses the first insulating layer (5) has a first opening (between 5), and the second insulating layer (81) has a second opening (81X).
Regarding claim 12, Kaneko discloses the first opening (between 5) overlaps the second opening (Figure 2).
Regarding claim 13, Kaneko discloses a part of the first metal layer (52) extends into the first opening (between 5) of the first insulating layer (5) and into the second opening (81X) of the second insulating layer (81).
Regarding claim 15 Kaneko discloses a bonding component (6) arranged to be disposed to correspond to the second metal layer (72).
Regarding claim 16, Kaneko discloses a side wall of the second metal layer (72) has a rough surface, and roughness of the rough surface of the side wall of the second metal layer is greater than or equal to 0.15 μm and less than or equal to 0.5 μm (paragraph 36).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (US Publication No. 2015/0008020) in view of Mun et al. (US Publication No. 2022/0068822), and further in view of Tsutsumi et al. (US Publication No. 2007/0272124).
Regarding claim 4, Kaneko discloses the limitations as discussed in the rejection of claim 1 above. Kaneko is silent regarding a dielectric loss coefficient of the first dielectric layer at 1 GHz is less than 0.01. However, Tsutsumi discloses a dielectric loss coefficient of a dielectric layer at 1 GHz to be less than 0.01 (Table 1). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the dielectric of Kaneko to has a loss coefficient in this range, as taught by Tsutsumi, since it can improve heat resistances and high frequency flexibility (paragraph 11), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (US Publication No. 2015/0008020) in view of Mun et al. (US Publication No. 2022/0068822), and further in view of Pietambaram et al. (US Publication No. 2023/0197697).
Regarding claim 14, Kaneko/Mun discloses the limitations as discussed in the rejection of claim 11 above. Kaneko/Mun is silent regarding a coefficient of thermal expansion of the first insulating layer is smaller than a coefficient of thermal expansion of the second insulating layer. However, Pietambaram discloses metal interconnects (146/150/144/192) surrounded by progressively smaller coefficient of thermal expansion insulating layers (102/127/104-1). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the insulating layers of Kaneko/Mun to have the first smaller than the second, as taught by Pietambaram, to minimize stress among the layers, thereby increasing the reliability of the device (paragraph 34).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (US Publication No. 2015/0008020) in view of Lin et al. (US Publication No. 2018/0006008).
Regarding claim 17, Kaneko discloses a method of manufacturing an electronic device, comprising:
providing a first electronic unit (3)
providing a first metal layer (52) respectively electrically connected to the first electronic unit (3)
providing a second metal layer (72) electrically connected to the first metal layer (52)
performing a first surface treatment to roughen surfaces of the first metal layer (52) and of the second metal layer (72) (paragraphs 71 and 79)
providing a first dielectric layer (82/60) to cover the first metal layer (52), the second metal layer (72)
removing a portion of the first dielectric layer (82/60) to expose the second metal layer (72) (Figure 2)
performing a second surface treatment to roughen exposed the second metal layer (paragraphs 71 and 79)
Kaneko does not disclose a second electronic unit with an encapsulation layer surrounding both the first and second electronic units. However, Lin discloses encapsulating first and second electronic units (424) (Figure 10I). It would have been obvious to one of ordinary skill in the art at a time before the effective filing of the invention to have modified the method of Kaneko to include forming and encapsulating multiple electronic units, as taught by Lin, since it can allow for improved manufacturing efficiency with reduced package profile (paragraph 11).
Regarding claim 18, Kaneko discloses the limitations as discussed in the rejection of claim 17 above. Kaneko also discloses providing a bonding component (6) overlapping the second metal layer (72); and forming an intermediate layer (flux) disposed between the bonding component (6) and the second metal layer (72) (paragraph 88); wherein in a cross-sectional view of the electronic device (Figure 1), a vertical distance between a top surface of the first dielectric layer (82/60) and a top surface of the first metal layer (52) along a normal direction of the electronic device is a first height, another vertical distance along the normal direction between a top surface of the second metal layer (72) and the top surface of the first metal layer (52) is a second height, the first height (82X) is greater than the second height (P2). Kaneko is silent regarding a difference between the first height and the second height is greater than or equal to 1 μm and less than or equal to 15 μm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kaneko’s height difference to be within this range to optimize device thickness against adhesion and alignment of the external connection, thereby improving reliability of the connection (paragraph 96), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 19, Kaneko discloses roughness of the top surface of the second metal layer (72) is formed in a second surface treatment, wherein roughness of the top surface of the second metal layer (72) is greater than or equal to 0.2 μm and less than or equal to 5 μm (paragraphs 71 and 79).
Regarding claim 20, Lin discloses cutting the encapsulation layer (468) to separate the first electronic unit (424 left) and the second electronic unit (424 right) (Figure 10R). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kaneko in view of Lin.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.R.P/ 7/26/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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