DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected product, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/4/2026.
Applicant’s election without traverse of claims 1-9 in the reply filed on 8/4/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Oshika (US 2009/0151982) in view of Liu (US 6,482,476).
With regards to claim 1, fig. 3 of Oshika discloses a method for fabricating a semiconductor module 10, the method comprising: providing a first metal layer 11; applying, by chemical vapor deposition (“CVD”, par [0074]), a ceramic layer 12 to the first metal layer 11; applying a second metal layer 13 at least in part to the ceramic layer 12; and attaching a semiconductor die 15 on a portion 13a of the second metal layer 13, wherein the ceramic layer 12 has a compressive stress in a range from 0.5 MPa to 20 MPa (“ thickness of the metal substrate 11 with the ease of its handling or the like taken into account is about 100 .mu.m to 1 mm whereas each of the ceramic layer 12, the electrode layer 13A and the solder layer 14 has its thickness generally of 10 .mu.m or less.”, par [0057]).
Oshida does not disclose apply by plasma enhanced chemical vapor deposition, a ceramic layer.
However, Liu discloses apply by plasma enhanced chemical vapor deposition (“plasma enhanced chemical vapor deposition”, abstract), a ceramic layer (“ceramic coatings”, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art to form the ceramic layer of Oshida with the PECVD as taught in Liu in order to provide a deposition process that is carried out at low temperature to prevent the bulk substrate properties from being adversely affected. See abstract of Liu.
With regards to claim 2, fig. 3 of Oshida discloses a material of the ceramic layer 12 comprises one or more of Si3N4, SiO or AlN (“AlN thin film as ceramic layer 12”, par [0074]), Zirconia doped alumina, SiAlON, or mixtures thereof or layerings thereof.
With regards to claim 3, fig. 3 of Oshida discloses applying the ceramic layer 12 to a thickness in a range from 10 µm (“10 um “, par [0057]) to 40 µm.
With regards to claim 4, fig. 3 of Oshida discloses a thickness ratio of the ceramic layer 12 to the first metal layer 11 is at least 1:5 (10 um to 100 um is 1:10 which is at least 1:15, par [0057]).
With regards to claim 5, fig. 3 of Oshida discloses that the ceramic layer 12 has a thermal resistance of less than 13 K/W (“0.03”, par [0058]) based on a one mm2 reference area.
With regards to claim 6, Oshida does not disclose a process temperature of the plasma enhanced chemical vapor deposition is below 400°C.
However, Liu discloses a process temperature of the plasma enhanced chemical vapor deposition (“plasma enhanced chemical vapor deposition”, abstract) is below 400°C (“<350 degC”, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art to form the ceramic layer of Oshida with the PECVD as taught in Liu in order to provide a deposition process that is carried out at low temperature to prevent the bulk substrate properties from being adversely affected. See abstract of Liu.
With regards to claim 7, fig. 3 of Oshida discloses an applied thickness of the second metal layer 13 is in a range from 10 µm (“10 um”, par [0057]) to 120 µm.
With regards to claim 9, fig. 3 of Oshida discloses the semiconductor die comprises one or more of a semiconductor transistor die (“transistor”, par [0054]), a power semiconductor transistor die, an IGBT, a MOSFET, a diode die, or a driver die.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Oshika (US 2009/0151982), Liu (US 6,482,476), and Tomizawa (US 2019/0326061).
With regards to claim 8, Oshika and Liu do not disclose that the second metal layer is applied by plasma enhanced chemical vapor deposition or by sputtering.
However, Tomizawa discloses that the second metal layer 14 is applied by plasma enhanced chemical vapor deposition or by sputtering (“first and second external electrodes 14 and 15 can be formed by, for example, performing sputtering”, par [0115]).
Therefore, it would have been obvious to one of ordinary skill in the art to deposit the electrodes of Oshika by sputtering as taught in Tomizawa in order to form external electrodes on a ceramic surface. See par [0117] of Tomizawa.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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