DETAILED ACTION
This Office action is in response to the application filed 14 March 2024. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-13, and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0367721 A1 to Jeong et al. (hereinafter “Jeong”).
Regarding independent claim 1, Jeong (Fig. 10A) discloses a semiconductor device comprising: a substrate 110 (¶ 0067; labeled in Fig. 9A); a bit line BL (¶ 0067) that extends in a first horizontal direction D1 on the substrate; a first mold layer 115/111/150 (¶¶ 0069-70, 0094; Figs. 9A, 9B) on the bit line, wherein the first mold layer defines a mold opening (CP disposed therein; ¶ 0070 - trenches) that exposes a portion of an upper surface of the bit line BL, and wherein the first mold layer extends in a second horizontal direction D2 (¶ 0071) that intersects the first horizontal direction; a channel layer CP (¶ 0071) on the bit line; one or more word lines WL (¶ 0077) that are on sidewalls of the channel layer and that extend in the second horizontal direction; and a gate insulating layer Gox (¶ 0079) between the one or more word lines WL and the channel layer CP, wherein the channel layer comprises a first oxide semiconductor layer BAL (¶ 0074), a second oxide semiconductor layer COL (¶ 0074), and an auxiliary channel layer (2DEG within COL, ¶ 0073) between the first oxide semiconductor layer and the second oxide semiconductor layer (¶ 0073).
Regarding claim 2, Jeong (Fig. 10A) discloses the semiconductor device of claim 1, wherein each of the first oxide semiconductor layer BAL and the second oxide semiconductor layer COL comprises indium gallium zinc oxide (IGZO) (¶ 0074).
Regarding claim 3, Jeong (Fig. 10A) discloses the semiconductor device of claim 1, wherein the auxiliary channel layer (within COL) comprises at least one of a two-dimensional (2D) material (¶ 0073 - 2DEG) and indium oxide (In.sub.2O.sub.3).
Regarding claim 5, Jeong (Figs. 10A, 9A-9B) discloses the semiconductor device of claim 1, wherein the first mold layer 115/111/150 comprises a lower first insulating layer 111 (¶ 0069; Fig. 9B) on the bit line BL, a second insulating layer 115 on the lower first insulating layer 111 (Fig. 9B), and an upper first insulating layer 150 on the second insulating layer 115 (Fig. 10A).
Regarding claim 6, Jeong discloses the semiconductor device of claim 5, wherein the lower first insulating layer 111 and the upper first insulating layer 150 comprise silicon nitride (¶ 0069), and the second insulating layer 115 comprises silicon oxide (¶ 0070).
Regarding claim 7, Jeong (Figs. 10A, 9A-9B) discloses the semiconductor device of claim 5, wherein, in a vertical direction D3, a thickness of the second insulating layer 115 is greater than a thickness of the lower first insulating layer 111 (Fig. 9B) and a thickness of the upper first insulating layer 150 (Fig. 9A).
Regarding claim 8, Jeong discloses the semiconductor device of claim 1, wherein a thickness of the first oxide semiconductor layer BAL and a thickness of the second oxide semiconductor layer COL are greater than a thickness of the auxiliary channel layer (2DEG within COL) (Fig. 10A).
Regarding claim 9, Jeong (Fig. 10A) discloses the semiconductor device of claim 1, wherein the channel layer CP is on an inner wall of the mold opening (Fig. 10A - CP disposed between portions of 115) or on the upper surface of the bit line BL (Fig. 10A).
Regarding claim 10, Jeong (Fig. 10A) discloses the semiconductor device of claim 1, wherein the channel layer CP extends on first and second inner walls of the mold opening (Fig. 10A - CP disposed between and on walls of 115) and on the upper surface of the bit line BL between the opposing first and second inner sidewalls (Fig. 10A).
Regarding claim 11, Jeong (Fig. 10A) discloses the semiconductor device of claim 1, wherein the one or more word lines WL comprise a first word line WL1 and a second word line WL2 spaced apart from each other in the first horizontal direction D1 in the mold opening (between portions of 115), and wherein the semiconductor device further comprises an insulating liner Gox (¶ 0090) and a first insulating layer 141 (¶ 0091) between the first word line and the second word line (Fig. 10A).
Regarding independent claim 12, Jeong (Fig. 10A) discloses a semiconductor device comprising: a substrate 110 (¶ 0067; labeled in Fig. 9A); a bit line BL (¶ 0067) that extends in a first horizontal direction D1 on the substrate; a first mold layer 115/111/150 (¶¶ 0069-70, 0094; Figs. 9A, 9B) on the bit line, wherein the first mold layer defines a mold opening (Fig. 10A - between portions of 115, CP disposed therein; ¶ 0070 - “trenches”) that exposes a portion of an upper surface of the bit line BL; a channel layer CP (¶ 0071) on an inner wall of the mold opening (Fig. 10A - between portions of 115), wherein the channel layer CP comprises a first oxide semiconductor layer BAL (¶ 0074) on the inner wall of the mold opening (Fig. 10A - between portions of 115) or on the bit line BL, an auxiliary channel layer (2DEG within COL, ¶ 0073) on the first oxide semiconductor layer BAL (¶ 0073), and the second oxide semiconductor layer COL (¶ 0073) on the auxiliary channel layer; a word line WL (¶ 0077) on sidewalls of the channel layer, wherein the word line extends in a second horizontal direction D2 that intersects the first horizontal direction D1; and a gate insulating layer Gox (¶ 0079) between the word line WL and the channel layer CP, wherein the auxiliary channel layer (2DEG within COL, ¶ 0073) comprises at least one of a two-dimensional (2D) material (¶ 0073 - 2DEG) and indium oxide (In.sub.2O.sub.3).
Regarding claim 13, Jeong (Fig. 10A) discloses the semiconductor device of claim 12, wherein each of the first oxide semiconductor layer BAL and the second oxide semiconductor layer COL comprises indium gallium zinc oxide (IGZO) (¶ 0074).
Regarding claim 15, Jeong (Figs. 10A, 9A-9B) discloses the semiconductor device of claim 12, wherein the first mold layer 115/111/150 comprises: a lower first insulating layer 111 (¶ 0069; Fig. 9B) on the bit line BL and comprising silicon nitride (¶ 0069); a second insulating layer 115 on the lower first insulating layer 111 (Fig. 9B) and comprising silicon oxide (¶ 0070), and an upper first insulating layer 150 on the second insulating layer 115 (Fig. 10A) and comprising silicon nitride (¶ 0069).
Regarding claim 16, Jeong (Figs. 10A, 9A-9B) discloses the semiconductor device of claim 15, wherein, in a vertical direction D3, a thickness of the second insulating layer 115 is greater than a thickness of the lower first insulating layer 111 (Fig. 9B) and a thickness of the upper first insulating layer 150 (Fig. 9A).
Regarding claim 17, Jeong discloses the semiconductor device of claim 12, wherein a thickness of the first oxide semiconductor layer BAL and a thickness of the second oxide semiconductor layer COL are greater than a thickness of the auxiliary channel layer (2DEG within COL) (Fig. 10A).
Regarding independent claim 18, Jeong (Fig. 10A) discloses a semiconductor device comprising: a substrate 110 (¶ 0067; labeled in Fig. 9A); a bit line BL (¶ 0067) that extends in a first horizontal direction D1 on the substrate; a first mold layer 115/111/150 (¶¶ 0069-70, 0094; Figs. 9A, 9B) on the bit line, wherein the first mold layer defines a mold opening (Fig. 10A - between portions of 115, CP disposed therein; ¶ 0070 - “trenches”) that exposes a portion of an upper surface of the bit line BL wherein the first mold layer 115/111/150 comprises a lower first insulating layer 111 (¶ 0069; Fig. 9B), a second insulating layer 115 on the lower first insulating layer 111 (Fig. 9B), and an upper first insulating layer 150 on the second insulating layer 115 (Fig. 10A);
a channel layer CP (¶ 0071) on an inner wall of the mold opening (Fig. 10A - between portions of 115), wherein the channel layer CP comprises a first oxide semiconductor layer BAL (¶ 0074) on the inner wall of the mold opening (Fig. 10A - between portions of 115) or on the bit line BL, an auxiliary channel layer (2DEG within COL, ¶ 0073) on the first oxide semiconductor layer BAL (¶ 0073), and a second oxide semiconductor layer COL (¶ 0073) on the auxiliary channel layer;
a word line WL (¶ 0077) on sidewalls of the channel layer, wherein the word line extends in a second horizontal direction D2 that intersects the first horizontal direction D1; a gate insulating layer Gox (¶ 0079) between the word line WL and the channel layer CP;
a capacitor structure DSP ( (Fig. 9A; ¶¶ 0095-96) on the first mold layer 115/111/150; and a contact layer LP (¶ 0095) between the channel layer CP and the capacitor structure DSP (Fig. 9A), wherein each of the lower first insulating layer 111 and the upper first insulating layer 150 comprise silicon nitride (¶ 0069), wherein the second insulating layer 115 comprises silicon oxide (¶ 0070), and wherein the auxiliary channel layer (2DEG within COL, ¶ 0073) comprises at least one of a two-dimensional (2D) material (¶ 0073 - 2DEG) and indium oxide (In.sub.2O.sub.3).
Regarding claim 19, Jeong (Fig. 10A) discloses the semiconductor device of claim 18, wherein each of the first oxide semiconductor layer BAL and the second oxide semiconductor layer COL comprises indium gallium zinc oxide (IGZO) (¶ 0074).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong.
Regarding claims 4, 14, and 20, Jeong (Fig. 10A) discloses the semiconductor device of claims 1, 12, and 18, however fails to expressly disclose: wherein a thickness of the auxiliary channel layer is less than 1 nm. Jeong does disclose the auxiliary channel is a 2DEG (¶ 0070) and thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above thickness, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the thickness is considered a result effective variable because it affects the mobility and concentration parameters of the 2DEG and thus the performance of the semiconductor device. Thus, the ordinary artisan would have been motivated to modify the 2DEG thickness for the purpose of adjusting the performance of the semiconductor device.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2023/0354605 to Kim et al., US 2023/0301067 A1 to Kim, US 2022/0223732 A1 to Ryu et al., US 2020/0212060 A1 to Yoo et al. disclosing semiconductor devices including multi-layer channels.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
20 July 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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