DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Owyang et al.( Owyang, US 2007/0063341 A1).
Regarding claim 1, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), comprising: a first power semiconductor die (IC 101 in FIG. 3B and [049]) arranged on and electrically coupled to a first side of a first die pad ( pad on element 102 in FIG. 3B); a first passive electronic component (L1 in FIG. 3B) comprising a first end (interface between element 101 and L1) and an opposite second end (opposite of interface between element 101 and L1), wherein the first end is arranged on and coupled to the first side of the first die pad and the second end is coupled to an internal ledge of a first external contact (Gnd/ Sw in FIG. 3B); a second passive electronic component ( element C4/C2 in FIG 3B) connected in series with the first passive electronic component (see FIG. 3B); and an encapsulation encapsulating the first power semiconductor die, the first passive electronic component, and the second passive electronic component ( see FIG. 3B with respect to FIG. 9A-9B and [0063-0064], wherein the first external contact is exposed from a first lateral side of the encapsulation ( see FIG. 3B with respect to FIG. 9A-9B and [0063-0064].
Regarding claim 2, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), further comprising: a second power semiconductor die (see FIG. 6 with respect to FIG. 3B i.e. bottom and top dies in FIG. 6) arranged on and electrically coupled to a second die pad, wherein the first power semiconductor die and the second power semiconductor die are electrically connected to form a half-bridge circuit (see FIG. 6 with respect to FIG. 3B i.e. bottom and top dies in FIG. 6).
Regarding claim 3, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), further comprising, wherein the second power semiconductor die is electrically connected to the first passive electronic component and the second passive electronic component (see FIG. 6 with respect to FIG. 3B i.e. bottom and top dies in FIG. 6).
Regarding claim 4, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the internal ledge of the first external contact (external contacts as shown in FIG. 3B and 6) is separated from the first die pad by a first trench (space between external contacts as shown in FIG. 6), and wherein the first passive electronic component ( C/C4 and L1) spans the first trench.
Regarding claim 5, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the first external contact is a power contact (see FIG. 6 i.e. VIN).
Regarding claim 6, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), further comprising: a second external contact ( see FIG. 3B with respect to FIG. 6 i.e. comprises plurality of contacts), wherein an internal ledge of the second external contact is separated from the internal ledge of the first external contact by a second trench, and wherein the second passive electronic component spans the second trench (see FIG. 3B with respect to FIG. 6).
Regarding claim 7, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the internal ledge of the second external contact has an L-shape ( lay out of element 110 in FIG. 3B) arranged along at least part of two lateral sides of the internal ledge of the first external contact ( external contacts as shown in FIG. 3B and 6).
Regarding claim 8, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), further comprising: a third external contact ( see FIG. 3B and 6 i.e. comprises plurality contacts); and a third passive electronic component ( C2/C4/L1), wherein an internal ledge of the third external contact is separated from the internal ledge of the second external contact by a third trench, and wherein the third passive electronic component spans the third trench (see FIG. 3B with respect to FIG. 6).
Regarding claim 9, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the internal ledge of the third external contact has an L-shape arranged along at least part of two lateral sides of the internal ledge of the second external contact (see FIG. 3B with respect to FIG. 6).
Regarding claim 10, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the first passive electronic component and the second passive electronic component are capacitors (C2/C4 in FIG. 3B), and wherein the third passive electronic component is a resistor ([0049]).
Regarding claim 11, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the first passive electronic component and the second passive electronic component are capacitors (C2/C4 in FIG. 3B).
Regarding claim 12, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the encapsulation comprises a molded body ( see FIG. 3B with respect to FIG. 9A-9B and [0063-0064]).
Regarding claim 13, Owyang shows a power semiconductor package (Package 100 in FIG. 3B and [0049]), wherein the internal ledge of the first external contact has an essentially rectangular shape, and wherein a longer side of the internal ledge of the first external contact is arranged perpendicular to the first lateral side of the encapsulation (see FIG. 3B with respect to FIG. 9A-9B and [0063-0064]).
Regarding claim 14, Owyang shows a method for fabricating a power semiconductor package ( package 100 in FIG. 3B and 6), the method comprising: arranging a first power semiconductor die ( die 101 in FIG. 3B) on a first side of a first die pad and electrically coupling the first semiconductor die to the first side of the first die pad (see FIG. 3B with respect to FIG. 6); providing a first passive electronic component (C2/C4) comprising a first end and an opposite second end such that the first end is arranged on and coupled to the first side of the first die pad and the second end is coupled to an internal ledge of a first external contact (contacts in FIG. 3B and 6); connecting a second passive electronic component in series with the first passive electronic component; and encapsulating the first power semiconductor die, the first passive electronic component, and the second passive electronic component with an encapsulation such that the first external contact is exposed from a first lateral side of the encapsulation (see FIG. 3B with respect to FIG. 9A-9B and [0063-0064]).
Regarding claim 15, Owyang shows a method for fabricating a power semiconductor package ( package 100 in FIG. 3B and 6), wherein the internal ledge of the first external contact (internal contact in FIG. 3B and 6) is separated from the first die pad by a first trench, and wherein the first passive electronic component spans the first trench (see FIG. 3B with respect to FIG. 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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