DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-13 and 18) in the reply filed on 7/1/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Non-elected claims 14-17 are hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Perez (US 20220098029), hereinafter Perez, in view of Gu (US 20160229688), hereinafter Gu.
Regarding claim 1, Perez (refer to Figures 1-4) teaches a semiconductor die (comprising 100, described as “sensor die 100” in para 17 – see Figures 1-3), comprising:
a top side (uppermost horizontal side of 100 in orientation of Figure 2);
a bottom side (lowermost part of 100 that contacts 200 in orientation of Figure 2; or alternatively lowermost part of 200 that is directly attached to 400 – see Figure 2) opposite to the top side; and
a side surface (outermost vertical surfaces of 100 or 100/200 in orientation of Figure 2) connecting the top side and the bottom side, the bottom side and a part of the side surface are attachable to a solid structure (200 or 300) by a die attach material (400 or any attachment material, described as “die attach 400” in para 37).
Perez does not teach that the side surface has “an attachment control element” defining “an attachment zone by the die attach material”; and/or “an exclusion zone that is not contacted by the die attach material”. Gu (US 20160229688) refer to markup of Figure 5 provided below; also see para 36) teaches a similar semiconductor device (SD) with a top side (SD-TS), a bottom side (SD-BS) and a side surface (SD-SS-1 and SD-SS-2) connecting the top side and the bottom side, wherein the bottom side (SD-BS) and a part of the side surface (SD-SS-2) are attachable to a solid structure (SS) by an attach material (such as solder - para 47 describes "sealing the space can be accomplished by applying sealing material or soldering material to the support structure faces", while para 36 describes “support members 90, 95”), the side surface has an attachment control element defining: ‘an attachment zone (SD-BS and SD-SS-2 that are contacted by solder corresponding to “support members 90, 95”) contacted by the attach material; and/or an exclusion zone (SD-SS-1) that is not contacted by the attach material. It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Perez to modify the die attach interface of side surfaces so that the side surface has “an attachment control element” defining “an attachment zone by the die attach material”; and/or “an exclusion zone that is not contacted by the die attach material”. The ordinary artisan would have been motivated to modify Perez for at least the purpose of providing a reliable hermetic seal and providing stress relief (para 5 and 37 of Gu; also see para 29).
PNG
media_image1.png
478
704
media_image1.png
Greyscale
Regarding claim 2, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, wherein the attachment control element (formed by attachment zones SD-BS and SD-SS-2) is a stop element that defines a maximum height of the die attach material (as the attach material is contained in the attachment control element part – see Figure 5 above).
Regarding claim 3, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 2, wherein the stop element forms a physical barrier (i.e. formed by physical surfaces SD-BS and SD-SS-2) between the attachment zone and the exclusion zone.
Regarding claim 4, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 2, wherein the stop element is formed as a step (i.e. by a horizontal surface SD-BS and an abutting vertical surface SD-SS-2) between a pair of vertical sections of the side surface.
Regarding claims 5-6, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, but does not specifically state that the attachment control element is formed “as a region with an increased wettability” for the die attach material “compared to a surface of the semiconductor die in an adjacent region” (as recited in claim 5), and (as recited in claim 6) that “the attachment control element is a functionalized surface in the region with the increased wettability”. However, Perez suggests that “die attach 400” may be solder (para 37) and Gu also teaches solder material for attachment, and it is known that increased wettability of die attach materials like solder helps better bonding of the die attach material, which is desirable for increased reliability. Further, Gu teaches disposing “soft material 85” (see par 36) on attachment surfaces, and similar soft material is the bonding material (para 36), which would increase the affinity for attaching to bonding material such as solder. teaches It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Perez so that the attachment control element is formed “as a region with an increased wettability” for the die attach material “compared to a surface of the semiconductor die in an adjacent region”, and as such “the attachment control element is a functionalized surface in the region with the increased wettability”. The ordinary artisan would have been motivated to modify Perez for at least the purpose of increasing reliability of the bond formed by the die attach material.
Regarding claims 7-8, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, wherein the attachment control element is formed as a region (SD-SS-1 which does not have “soft material 85” described in para 36 and referenced in rejection of claim 5-6 above) with a decreased wettability for the die attach material (because of absence of 85) compared to a surface of the semiconductor die in an adjacent region (as recited in claim 7), and as such (as recited in claim 8), the attachment control element is a functionalized surface in the region with the decreased wettability. Thus, obviousness of claims 7-8 is substantially for the same reasons and same motivation as claim 5-6, except it is used to create areas of no bonding.
Regarding claim 9, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, wherein the bottom side (see SD-BS which is covered by 85, as explained for claims 5-6) has a functionalized surface (i.e. functionalized for better bonding, as explained for claims 5-6).
Regarding claim 10, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, wherein the bottom side has a spacer (marked “spacer” in markup of Figure 5 of Perez) spacing a bottom surface (SD-BS) of the semiconductor die apart from the solid structure (SS).
Regarding claim 11, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, but does not teach further comprising “a membrane”. However, Perez teaches that the semiconductor die may be a sensor comprising piezoresistive elements (see para 17), such as a pressure sensor (para 17), noting that Gu also teaches pressure sensor device (para 29), and it is known in the art that pressure sensors may use membranes to sense pressure. It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Perez to further comprise “a membrane”. The ordinary artisan would have been motivated to modify Perez for at least the purpose of using a membrane-type pressure sensor, where pressure changes cause membrane to move.
Regarding claims 12-13, Perez, as modified above in view of Gu, teaches the semiconductor die of claim 1, wherein the semiconductor die has a cross-sectional shape with a pair of legs (lowermost part that is attached to and nearest to the solid structure; see markup of Figure 5 of Gu) and a web (uppermost part that includes SD-TS; see markup of Figure 5) connecting the legs at a right angle. As such. It can be seen from Figure 5 markup that (as recited in claim 13) the top side (comprising SD-TS in markup of Figure 5) forms the web and a pair of outer sides of the legs each have the side surface (SD-SS-2 in markup of Figure 5).
Regarding claim 18, Perez (refer to Figures 1-4) teaches a MEMS-sensor device (para 17 describes device may “MEMS sensing device”), comprising:
a semiconductor die (100) including: a top side (uppermost horizontal side of 100 in orientation of Figure 2);
a bottom side (lowermost part of 100 that contacts 200 in orientation of Figure 2; or alternatively lowermost part of 200 that is directly attached to 400 – see Figure 2) opposite to the top side;
a side surface (outermost vertical surfaces of 100 or 100/200 in orientation of Figure 2) connecting the top side and the bottom side, the bottom side and a part of the side surface are attachable to a solid structure (200 or 300) by a die attach material (400 or any attachment material, described as “die attach 400” in para 37); and
a plurality of piezoresistive elements (para 17 describes “piezoresistive device” is part of 100).
Perez does not teach that the side surface has “an attachment control element” defining: “an attachment zone contacted by the die attach material”; and/or “an exclusion zone that is not contacted by the die attach material”. This limitation has already been addressed for claim 1 in view of Gu.
Further, Perez does not teach that the plurality of piezoresistive elements contain “a membrane”. This limitation is substantially similar to that has already been addressed for claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 5712721736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AJAY ARORA/Primary Examiner, Art Unit 2892
Prosecution Insights