DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/1/2025, 8/6/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion", “on”, “between” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently discloses a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “a function word to indicate position in close proximity with” “in the intervening space” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Te-Yin (US 2021/0408005 A1 hereinafter Chen) in view of Noh et al (US 2020/0381436 A1 hereinafter Noh).
Regarding Claim 1, Chen discloses in Fig 2-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (AA) in a substrate (100);
forming a recess gate structure (104) in the substrate, wherein the
recess gate structure intersects the active region (AA);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (BC) in the at least one dielectric layer;
forming a bit line (BL) over the bit line contact and in an additional
dielectric layer (top most 110);
forming a contact structure (CC) on the substrate, wherein the contact structure is located at a side of the recess gate structure, and is electrically connected to the active region (AA);
sequentially forming a first conductive (118) layer and a second conductive layer (118) over the substrate, wherein the contact structure is covered by the first and second conductive layers;
forming a conductive pillar (116) and a landing pad (CP) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure (CC), the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3N); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3N) [0042-0057].
wherein the recess gate structure is formed by:
conformally forming a gate insulating layer (106) in a trench disposed in the substrate at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0036];
wherein a top surface of the gate insulating layer (106), a top surface of the capping layer (108), and a top surface of the substrate (100) are coplanar with each other.
Chen does not disclose: forming a work function layer on the gate insulating layer and in the trench;
forming a first conductive layer on the work function layer and in the trench; and
forming a capping layer on the first conductive layer and in the trench;
wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer;
However, Noh in a similar device teaches in Fig 6D-6H: forming a work function layer (124) on the gate insulating layer and in the trench;
forming a first conductive layer (126) on the work function layer and in the trench; and
forming a capping layer (128) on the first conductive layer and in the trench;
wherein the word function layer (124), the first conductive layer (126), and the capping layer (128) are surrounded by the gate insulating layer (120) [0029-0034].
References Chen and Noh are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Noh because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Noh so that forming a work function layer on the gate insulating layer and in the trench; forming a first conductive layer on the work function layer and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer as taught by Noh in Chen’s method since, this provides a novel technique for precisely controlling the threshold voltage of the gate electrode and enhancing the reliability of the integrated circuit device.
Regarding Claim 2, Chen and Noh disclose: The method of claim 1, Chen discloses in Fig 2-3N: wherein the formation of the landing pad is performed by a first etching process [S27 0051].
Regarding Claim 3, Chen and Noh disclose: The method of claim 2, Chen discloses in Fig 2-3N: wherein the formation of the conductive pillar is performed by the first etching process and sequentially by a second etching process [0051].
Regarding Claim 4, Chen and Noh disclose: The method of claim 3, Chen discloses in Fig 2-3N: wherein the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process [0007-0008].
Regarding Claim 5, Chen and Noh disclose: The method of claim 1, Chen discloses in Fig 2-3N: further comprising: forming a capacitor plug (PG) disposed over and electrically connected to the landing pad (S33) [0027].
Regarding Claim 6, Chen and Noh disclose: The method of claim 5, Chen discloses in Fig 2-3N: further comprising: forming a storage capacitor (SC) disposed over and electrically connected to the capacitor plug (S35, S37, S39).
Claim(s) 1, 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Te-Yin (US 2021/0408005 A1 hereinafter Chen) in view of Lee et al (US 2017/0365608 A1 hereinafter Lee).
Regarding Claim 1, Chen discloses in Fig 2-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (AA) in a substrate (100);
forming a recess gate structure (104) in the substrate, wherein the
recess gate structure intersects the active region (AA);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (BC) in the at least one dielectric layer;
forming a bit line (BL) over the bit line contact and in an additional
dielectric layer (top most 110);
forming a contact structure (CC) on the substrate, wherein the contact structure is located at a side of the recess gate structure, and is electrically connected to the active region (AA);
sequentially forming a first conductive (118) layer and a second conductive layer (118) over the substrate, wherein the contact structure is covered by the first and second conductive layers;
forming a conductive pillar (116) and a landing pad (CP) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure (CC), the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3N); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3N) [0042-0057].
wherein the recess gate structure is formed by:
conformally forming a gate insulating layer (106) in a trench disposed in the substrate at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0036];
wherein a top surface of the gate insulating layer (106), a top surface of the capping layer (108), and a top surface of the substrate (100) are coplanar with each other.
Chen does not disclose: forming a work function layer on the gate insulating layer and in the trench;
forming a first conductive layer on the work function layer and in the trench; and
forming a capping layer on the first conductive layer and in the trench;
wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer;
However, Lee in a similar device teaches in Fig 10: forming a work function layer (146) on the gate insulating layer (120) and in the trench;
forming a first conductive layer (144) on the work function layer and in the trench; and
forming a capping layer (136) on the first conductive layer and in the trench;
wherein the word function layer (146), the first conductive layer (144), and the capping layer (136) are surrounded by the gate insulating layer (120) [0102].
References Chen and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Lee so that forming a work function layer on the gate insulating layer and in the trench; forming a first conductive layer on the work function layer and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 7, Chen and Lee disclose: The method of claim 1.
Chen does not disclose: wherein the recess gate structure further comprises:
conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer;
wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein.
However, Lee in a similar device teaches in Fig 10: wherein the recess gate structure further comprises: conformally disposing a liner layer (149_s) on the first conductive layer (144) and on the gate insulating layer (120), and disposed between the capping layer (136) and the first conductive layer (144); and disposing a second conductive layer (148) between the capping layer and the liner layer; wherein the liner layer (149_s) is formed in a U-shaped cross-sectional profile for the second conductive layer (148) disposing therein [0102].
References Chen and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Lee so that the recess gate structure further comprises: conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer; wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 8, Chen and Lee disclose: The method of claim 7.
Chen does not disclose: wherein a top surface of the liner layer is coplanar with a bottom surface of the capping layer.
However, Lee in a similar device teaches in Fig 10: wherein a top surface of the liner layer (149_s) is coplanar with a bottom surface of the capping layer (136) [0102].
References Chen and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Lee so that a top surface of the liner layer is coplanar with a bottom surface of the capping layer as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 9, Chen and Lee disclose: The method of claim 8.
Chen does not disclose: wherein a top surface of the second conductive layer, the top surface of the liner layer, and the bottom surface of the capping layer are coplanar.
However, Lee in a similar device teaches in Fig 10: wherein a top surface of the second conductive layer (148), the top surface of the liner layer (149_s), and the bottom surface of the capping layer (136) are coplanar [0102].
References Chen and Lee are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Lee so that a top surface of the second conductive layer, the top surface of the liner layer, and the bottom surface of the capping layer are coplanar as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Claim(s) 1, 7, 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Te-Yin (US 2021/0408005 A1 hereinafter Chen) in view of Huang, Tse-Yao (US 2024/0222370 A1 hereinafter Huang).
Regarding Claim 1, Chen discloses in Fig 2-3N: A method for fabricating a semiconductor device, comprising:
forming an active region (AA) in a substrate (100);
forming a recess gate structure (104) in the substrate, wherein the
recess gate structure intersects the active region (AA);
forming at least one dielectric layer (110) on the substrate;
forming a bit line contact (BC) in the at least one dielectric layer;
forming a bit line (BL) over the bit line contact and in an additional
dielectric layer (top most 110);
forming a contact structure (CC) on the substrate, wherein the contact structure is located at a side of the recess gate structure, and is electrically connected to the active region (AA);
sequentially forming a first conductive (118) layer and a second conductive layer (118) over the substrate, wherein the contact structure is covered by the first and second conductive layers;
forming a conductive pillar (116) and a landing pad (CP) over the substrate, wherein the conductive pillar overlaps and electrically connects to the contact structure (CC), the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad (See Fig 3N); and
forming a dielectric layer (110d) to laterally surround the conductive pillar and the landing pad (See Fig 3N) [0042-0057].
wherein the recess gate structure is formed by:
conformally forming a gate insulating layer (106) in a trench disposed in the substrate at a position that the gate insulating layer is formed on side surfaces and a bottom surface of the trench (See Fig 3B) [0036];
wherein a top surface of the gate insulating layer (106), a top surface of the capping layer (108), and a top surface of the substrate (100) are coplanar with each other.
Chen does not disclose: forming a work function layer on the gate insulating layer and in the trench;
forming a first conductive layer on the work function layer and in the trench; and
forming a capping layer on the first conductive layer and in the trench;
wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer;
However, Huang in a similar device teaches in Fig 1-16: forming a work function layer (313) on the gate insulating layer (311) and in the trench;
forming a first conductive layer (317) on the work function layer and in the trench; and
forming a capping layer (323) on the first conductive layer and in the trench;
wherein the word function layer (313), the first conductive layer (317), and the capping layer (323) are surrounded by the gate insulating layer (311) [0087-0089].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so that forming a work function layer on the gate insulating layer and in the trench; forming a first conductive layer on the work function layer and in the trench; and forming a capping layer on the first conductive layer and in the trench; wherein the word function layer, the first conductive layer, and the capping layer are surrounded by the gate insulating layer as taught by Lee in Chen’s method since, this provides a semiconductor device’s gate structure with a low resistance [0007].
Regarding Claim 7, Chen and Huang disclose: The method of claim 1.
Chen does not disclose: wherein the recess gate structure further comprises:
conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer;
wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein.
However, Huang in a similar device teaches in Fig 10: wherein the recess gate structure further comprises: conformally disposing a liner layer (319) on the first conductive layer (317) and on the gate insulating layer (311), and disposed between the capping layer (323) and the first conductive layer (317); and disposing a second conductive layer (321) between the capping layer and the liner layer; wherein the liner layer (319) is formed in a U-shaped cross-sectional profile for the second conductive layer (321) disposing therein [0059].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so that the recess gate structure further comprises: conformally disposing a liner layer on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and disposing a second conductive layer between the capping layer and the liner layer; wherein the liner layer is formed in a U-shaped cross-sectional profile for the second conductive layer disposing therein as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 10, Chen and Huang disclose: The method of claim 7.
Chen does not disclose: wherein the liner layer is formed of a material having an etching selectivity to the gate insulating layer.
However, Huang in a similar device teaches in Fig 10: wherein the liner layer (319) is formed of a material having an etching selectivity to the gate insulating layer (311) [0059].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so that the liner layer is formed of a material having an etching selectivity to the gate insulating layer as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 11, Chen and Huang disclose: The method of claim 10.
Chen does not disclose: wherein the liner layer is formed of a material including sp² hybridized carbon atoms.
However, Huang in a similar device teaches in Fig 10: wherein the liner layer (319) is formed of a material including sp² hybridized carbon atoms [0061].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so wherein the liner layer is formed of a material including sp² hybridized carbon atoms as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 12, Chen and Huang disclose: The method of claim 7.
Chen does not disclose: wherein the second conductive layer is formed of molybdenum.
However, Huang in a similar device teaches in Fig 10: wherein the second conductive layer (321) is formed of molybdenum [0066].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so the second conductive layer is formed of molybdenum as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor.
Regarding Claim 13, Chen and Huang disclose: The method of claim 12.
Chen does not disclose: wherein the second conductive layer is formed by a chemical vapor deposition process.
However, Huang in a similar device teaches in Fig 10: wherein the second conductive layer (321) is formed by a chemical vapor deposition process [0066].
References Chen and Huang are analogous art because they both are directed to manufacturing methods of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Chen with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Chen and Huang so that the second conductive layer is formed by a chemical vapor deposition process as taught by Lee in Chen’s method since, this provides a semiconductor device capable of reducing a leakage current of a transistor and CVD is a commonly used deposition process for metal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811
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