DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: INTEGRATED CIRCUIT DEVICES WITH STACKED GATE ELECTRODES
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jung (US 20210398998), hereinafter Jung.
Regarding claim 1 Jung (US 2021I0398998A1) teaches an integrated circuit device (100 of figure 2 A is designated as a semiconductor device in para 26, but is also an integrated circuit device) comprising:
a substrate (101, Para 26);
a stack structure (GS, para 26) comprising interlayer insulating layers (120, para 26) and gate electrodes (130, para 26) stacked (in the vertical or Z directIon, para 26) alternately with the interlayer insulating layers on the substrate;
a channel structure (CH, described as penetrating through the stack structure GS, para 26) comprising a core pattern (150, para 32 and figure 2A), a pad structure on the core pattern (PAD, para 33 and 39), and a channel layer (140, para 39) on a side surface of the core pattern and a side surface of the pad structure, wherein the channel structure is in the stack structure;
a plug (170, para 26)on the channel structure (CH, para 26); and a bit line(180, para 26) on the plug (170, para 26),
wherein the gate electrodes (130, para 26 and para 28, where it is described as gate electrodes 130 that are alternately and repeatedly stacked in the vertical direction Z) comprise a first upper gate electrode (130(U1), para 31 and 33) at a highest position among the gate electrodes relative to the substrate and a second upper
gate electrode at a second-highest position among the gate electrodes relative to the substrate(130(U2J, para 31 and 33),
the second upper gate electrode is directly adjacent to the first upper gate electrode in a vertical direction perpendicular to an upper surface of the substrate (130(U1 and (U2), para 33 where the arrangement is described as "The first upper gate
electrode 130(U1) may be disposed on the second upper gate electrode 130(U2)"),
the interlayer insulating layers (120, para 26 and figure 2A) comprises a first interlayer insulating layer that is between the first upper gate electrode (130(U1)), and the second upper gate electrode (130(U2)), and has a first thickness in the vertical direction (120, para 28-29, figure 2 A),
the first thickness is different from a second thickness of a second interlayer insulating layer of the interlayer insulating layers in the vertical direction (120, para 28-29, figure 2 A where it is described as " interlayer insulating layer 120U of the interlayer insulating layers 120 may have a thickness greater than
the thickness of each of the other interlayer insulating layers), and a lower surface of the pad structure (PAD) is distant from the substrate (101) by a first distance (see figure 2A),
a lower surface of the first upper gate electrode (130(U1)) is distant from the substrate by a second distance that is longer than or equal to the first distance (see figure 2 A), and an upper surface of the second upper gate electrode (130(U2)) is distant from the substrate by a third distance that is shorter than or equal to the first distance (see figure 2 A).
[AltContent: ]
Regarding claim 2 Jung teaches the integrated circuit device of claim 1, wherein the first thickness is greater than the second thickness (120, para 28-29, figure 2 A where it is described as "interlayer insulating layer 120U of the interlayer insulating
layers 120 may have a thickness greater than the thickness of each of the other interlayer insulating layers, also see para 81).
Regarding claim 3 Jung teaches the integrated circuit device of claim 1, wherein the first thickness is in a range from about 380 angstroms (A) to about 500 A. (para 47)
Regarding claim 4 Jung teaches the integrated circuit device of claim 1, wherein at least one of the first upper gate electrode and the second upper gate electrode has a third thickness in the vertical direction different from a fourth thickness of one gate electrode of the gate electrodes in the vertical direction ( para 33 and description of figure 2 A or figure 8).
Regarding claim 5 Jung teaches the integrated circuit device of claim 1, wherein the first upper gate electrode ((130(U1)) and the second upper gate electrode ((130(U2)) comprise erase gate electrodes (Para 33).
Regarding claim 6 Jung teaches the integrated circuit device of claim 1, wherein the first upper gate electrode has a third thickness in the vertical direction ( see figure 2A where 130 U1 thicknesss is shown),
wherein one electrode of the gate electrodes has a fourth thickness in the vertical direction( para 33, figure 2A), and
a sum of the third thickness and the first thickness and a sum of the fourth thickness and the second thickness ( see figure 2A),
Regarding claim 7 Jung teaches the integrated circuit device (100 of figure 2 A is designated as a semiconductor device in para 26, but is also an integrated circuit device) of claim 1, wherein the pad structure (para 7) comprises:
a pad pattern (para 7);
a first pad layer (153, para 46, figure 2A, Figure 8) between the channel layer (140, para 46 figure 2A, Figure 8) and the pad pattern (150, para 46 figure 2A, Figure 8); and
a second pad layer (152, para 46, figure 2A, Figure 8) comprising a first portion
(152a, para 46) and a second portion (152b, para 46),
wherein the first portion (152a, para 46) is between the channel layer (140) and the first pad layer (153), and the second portion is between the first pad layer (153) and the core pattern (140).
Regarding claim 8 Jung teaches the integrated circuit device (100 of figure 2 A and figure 8 is designated as a semiconductor device in para 26, but is also an integrated circuit device)of claim 7,
wherein the pad pattern (155) has a first conductive type (para 48), and the first pad layer (153) has a second conductive type (para 49) that is different from the first conductive type (para 49).
Regarding claim 9 Jung teaches the integrated circuit device (100 of figure 2 A and figure 8 is designated as a semiconductor device in para 26, but is also an integrated circuit device) of claim 7,
wherein a lower surface of the pad pattern is distant from the substrate by a fourth distance (para 5 where it is disclosed that pad pattern has a distance from substrate, figure 2A), the lower surface of the first upper gate electrode (130U1) is distant from the substrate by a fifth distance (figure 2A clearly shows that 130 U1 has a distance from substrate, figure 2A) that is longer than or equal to the fourth distance, and the upper surface of the second upper gate electrode(130U2) is distant from the substrate by a sixth distance that is shorter than or equal to the fourth distance, figure 2A clearly shows that 130 U1 has a distance from substrate, also see
figure 8).
Regarding claim 10 Jung teaches the integrated circuit device (100 of figure 2 A) of claim 7,
wherein at least a portion of the first upper gate electrode overlaps the pad structure in a first horizontal direction (para 33).
Regarding claim 11 Jung teaches the integrated circuit device (100 of figure 2 A is designated as a semiconductor device in para 26, but is also an integrated circuit device) comprising:
a substrate(101, Para 26);
a stack structure (GS, para 26) comprising interlayer insulating layers (120, para 26) and gate electrodes (130, para 26) stacked (in the vertical or Z directon, para 26) alternately with the interlayer insulating layers on the substrate;
a channel structure in the stack structure (CH, described as penetrating through the stack structure GS, para 26);
a plug (170, para 26)on the channel structure (CH, para 26); and a bit line (180, para 26) on the plug (170, para 26),
a channel structure (CH, described as penetrating through the stack �tru�turo GS, para 26) comprising a core pattern (150, para 32 and figure 2A), a pad structure on the core pattern(PAD, para 33 and 39), and a channel layer (140, para 39) on a side surface of the core pattern and a side surface of the pad structure;
a first upper gate electrode (130(U1), para 31 and 33) at a highest position (figure 2A) among the gate electrodes relative to the substrate comprises an erase gate electrode (Para 33),
a first thickness in a vertical direction of a first interlayer insulating layer (120, para 26 and figure 2A) of the interlayer insulating layers is different from a second thickness in the vertical direction of a second interlayer insulating layer of the interlayer insulating layers(120, para 28-29 and figure 2A) ,
the first interlayer insulating layer is between the first upper gate electrode and the second interlayer insulating layer (120, para 28, 29 and figure 2A) , and
the vertical direction is perpendicular to an upper surface of the substrate (Para 28 figure 2A).Regarding claim 12 Jung teaches the integrated circuit device (100 of figure 2 A or figure 8) of claim 11,
wherein the first thickness is greater than the second thickness ( figure 2 A.
[AltContent: ]Regarding claim 13 Jung teaches the integrated circuit device (100 of figure 2 A or figure 8) of claim 11,
wherein at least a portion of the first upper gate electrode overlaps the pad structure in a first horizontal direction perpendicular to the vertical direction (para 33).
Regarding claim 14 Jung teaches the integrated circuit device (100 of figure 2 A or figure 8) of claim 11,
wherein a third thickness of the first upper gate electrode in the vertical direction is different from a fourth thickness one gate electrode of the gate electrodes in the vertical direction( thickness of upper gate electrodes discussed in para 33 and shown in figure 2 A or figure 8).
Regarding claim 15 Jung teaches the integrated circuit device (100 of figure 2 A or figure 8) of claim 11,
wherein the pad structure comprises a pad pattern (155), a first pad layer (153) between the channel layer and the pad pattern, and a second pad layer comprising a first portion and a second portion (Para 46),
wherein the first portion is between the channel layer and the first pad layer (153), and wherein the second portion is between the first pad layer and the core pattern ( details in para 46).
Regarding claim 16 Jung teaches the integrated circuit device of claim 15,
wherein the pad pattern (155, para 46) has a first conductive type, and the first pad layer has a second conductive type (para 49) that is different from the first conductive type (para 49).
Regarding claim 17 Jung teaches the integrated circuit device (100 of figure 2 A is designated as a semiconductor device in para 26, but is also an integrated circuit device) comprising:
a first substrate(101, para 72 figure 8);
circuit devices on the first substrate (para 72);
a second substrate on the circuit devices (Para 72, figure 8);
a stack structure (para 71 and figure 8) comprising interlayer insulating layers ( para 75) and gate electrodes (225, para 74) stacked (in the vertical or Z direction, para 71, described as stacked vertically, figure 8) alternately with the interlayer insulating layers on the second substrate in a vertical direction perpendicular to an upper surface of the second substrate (see figure 8); and
a channel structure in the stack structure CH, described as penetrating through the stack structure GS, para 26 also note similar features in figure 8 and para 78), the channel structure comprising a channel layer (140, para 78), a core pattern on a side surface of the channel layer(core 150, para 32 and figure 2Aas well as figure 8), and a pad structure on the core pattern (PAD, Para 33, 39 and figure 8. And para 85-86),
wherein the gate electrodes (130, para 26 and para 28, where it is described as gate electrodes 130 that are alternately and repeatedly stacked in the vertical direction Z, also see figure 8) comprise a first upper gate electrode 130(U1), para 31 and 33, also see figure 8) at a highest position among the gate electrodes relative to the second substrate and a second upper gate electrode at a second-highest position among the gate electrodes relative to the second substrate(130(U2), para 31 and 33, also see figures 2A and 8),
a first thickness of a first interlayer insulating layer of the interlayer insulating layers in the vertical direction is different from a second thickness of a second interlayer insulating layer of the interlayer insulating layers in the vertical direction (120, para 28-29, figure 2 A where it is described as "interlayer insulating layer 120U of the interlayer insulating layers 120 may have a thickness greater than
the thickness of each of the other interlayer insulating layers, similar structure and features are shown in figure 8 as we/f),
the first interlayer insulating layer (120, para 26, 28 and 78 and 81, figures 2A and 8) is between the first upper gate electrode and the second upper gate electrode, and
a lower surface of the pad structure is distant from the second substrate by a first distance (see Figure 8), a lower surface of the first upper gate electrode (130(U1), para 31 and 33, Figure 8) is distant from the second substrate by a second distance that is longer than or equal to the first distance (see figure 8 where first substrate 101 and second substrate 201 are clearly shown), and an upper surface of the second upper
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gate electrode is distant from the second substrate by a third distance that is shorter than or equal to the first distance (see figure 8).
(100 of figure 2 A is designated as a semiconductor device in para 26, but is also an integrated circuit device) comprising:
a substrate (101, Para 26);
Regarding claim 18 Jung teaches the integrated circuit device of claim 17,
wherein the first upper gate electrode ((130(U1)) and the second upper gate electrode ((130(U2)) comprise erase gate electrodes (Para 33).
Regarding claim 19 Jung teaches the integrated circuit device of claim 17,
wherein the first thickness is greater than the second thickness(120, para 28-29, figure 2 A where it is described as "interlayer insulating layer 120U of the interlayer insulating layers 120 may have a thickness greater than
the thickness of each of the other interlayer insulating layers).
Regarding claim 20 Jung teaches the integrated circuit device of claim 17,
wherein at least a portion of the first upper gate electrode (130 U1, figure 8 or figure 2A) overlaps the pad structure in a first horizontal direction perpendicular to the vertical direction ( as seen in figures 8 and 2 A but as stated in para 33, where it is disclosed that first upper gate electrode 130(U1) may overlap the pad structure PAD in the horizontal direction X).
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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