DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 25-26 are objected to because of the following informalities:
In claim 25 ll. 3 after “die cavity” insert –in--.
In claim 26 ll. 3 after “die cavity” insert –in--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 5 ll. 7, it is indefinite as to whether the “first direction” is meant to be the “first” or “second” direction. The first direction would be the left to right direction and second direction would be the top to bottom direction. For purposes of examination the later interpretation will be used.
In claim 10 ll. 2 and ll. 5, it is indefinite as to whether the “first direction” is meant to be the “first or “second” direction. The first direction would be the left to right direction and second direction would be the top to bottom direction. For purposes of examination the later interpretation will be used.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8, 10-18, 20, 22-25, and 29-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (US 2020/0105544).
With regards to claim 1, figs. 55-56 of Tsai discloses an interposer substrate 100, comprising: a first metallization layer 106 extending in a first direction (left to right), the first metallization layer 106 comprising: a plurality of first metal interconnects (leftmost and rightmost 106); and one or more second metal interconnects (two middle 106) each comprising a first surface (bottom of 106 in 124c); an outer layer 124 adjacent to the first metallization layer 106 in a second direction (top to bottom) orthogonal to the first direction (left to right), the outer layer 124 comprising: an outer insulating layer 124 comprising a plurality of outer metal interconnects 126 each coupled to a first metal interconnect (leftmost and rightmost 106) of the plurality of first metal interconnects 106; and a die cavity 124c in at least a portion of the outer insulating layer 124 adjacent to a first surface (bottom of 106) of each of the one or more second metal interconnects (two middle 106) in the second direction (top to bottom).
With regards to claim 2, figs. 55-56 of Tsai discloses at least a portion of the first surface (bottom of 106 above 124c) of the one or more second metal interconnects (two middle 106) is exposed to the die cavity 124c.
With regards to claim 3, figs. 55-56 of Tsai the one or more second metal interconnects (middle 106) comprise a metal (“copper”, par [0021]) plate.
With regards to claim 4, figs. 55-56 of Tsai discloses that the first metallization layer 106 comprises a third surface (top of 106) and a fourth surface (bottom of 106) opposite the third surface (top of 106) in the second direction (top to bottom), the third surface (top of 106) adjacent to the die cavity 124c and intersecting the die cavity 124c in the second direction (top to bottom); and the first surface (bottom of 106 above 124c) of the one or more second metal interconnects (two middle 106) are co-planar with the fourth surface (bottom of 106) in the first direction (left to right).
With regards to claim 6, figs. 55-56 of Tsai discloses that the outer layer 124 comprises a solder resist layer (“Solder resist layers 124”, par [0042]); the plurality of outer metal interconnects 126 comprises a plurality of metal posts 126; and the solder resist layer 124 comprises a plurality of first openings (“Openings may be made in the solder resist layers 124”, par [0056]) each adjacent to a metal post 126 of the plurality of metal posts 126.
With regards to claim 7, figs. 55-56 of Tsai discloses that the plurality of metal posts 126 do not intersect the die cavity 124c in the second direction (top to bottom).
With regards to claim 8, figs. 55-56 of Tsai discloses that the plurality of first metal interconnects (leftmost and rightmost 106) do not intersect the die cavity 126c in the second direction (top to bottom).
With regards to claim 10, figs. 55-56 of Tsai discloses that a second metallization layer 113 adjacent to the first metallization layer 106 in the [second] direction (top to bottom), wherein: the first metallization layer 106 is between the outer layer 124 and the second metallization layer 113 in the [second] direction (top to bottom); and the second metallization layer 113 comprises a plurality of third metal interconnects (leftmost and rightmost 113) each coupled to a first metal interconnect (leftmost and rightmost 106) of the plurality of first metal interconnects 106.
With regards to claim 11, figs. 55-56 of Tsai discloses that wherein the first metallization layer 106 comprises an embedded trace substrate (ETS) metallization layer 106 comprising a first insulating layer 110, the plurality of first metal interconnects 106 comprising a plurality of first metal traces 106 embedded in the first insulating layer 110.
With regards to claim 12, figs. 55-56 of Tsai discloses that the one or more second metal interconnects (106, 116) comprise a plurality of second vias 116.
With regard to claim 13, figs. 61-62 of Tsai discloses that the first insulating layer 110 further comprises: a non-recessed layer portion 306A comprising the plurality of first metal traces 106 and having a first height (height of 110 at 306A) in the second direction (top to bottom); and a recessed layer portion 306B comprising the one or more second metal interconnects 120 and forming a recessed region 130 adjacent to the first surface (bottom of 120) of the one or more second metal interconnects 120, the recessed layer portion 306B having a second height (height of 110 at 306B) in the second direction (top to bottom) less than the first height (height of 110 at 306A); and the die cavity 130 further comprising the recessed region 130.
With regards to claim 14, figs. 55-56 of Tsai discloses that the first insulating layer 110 comprises a step structure (sidewall of 130) formed in a first portion of the non-recessed layer portion (110 in 306A) adjacent to a second portion of the recessed layer portion (130 in 306B) in the first direction (left to right).
With regards to claim 15, figs. 61-62 of Tsai discloses that the die cavity 130 is adjacent to the step structure (sidewall of 130).
With regards to claim 16, figs. 61-62 of Tsai discloses that the first metallization layer comprises a metallization layer 106 comprising a first insulating layer 110, the plurality of first metal interconnects 106 adjacent to the first insulating layer 110.
Tsai does not disclose a modified semi-additive process (mSAP).
Applicant's claim 16 do not distinguish over the Tsai reference regardless of the process used to form the first metallization layer because only the final product is relevant, not the process of making such as a modified semi-additive process (mSAP).
Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps. See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Once a product appearing to be substantially identical is found and a 35 U.S.C. 102/103 rejection made, the burden shifts to the applicant to show an unobvious difference. See In re Fessmann, 489 F.2d 742, 744, 180 USPQ 324, 326 (CCPA 1974), In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983), and Ex parte Gray, 10 USPQ2d 1922 (Bd. Pat. App. & Inter. 1989). The use of 35 U.S.C. 102/103 rejections for product-by-process claims has been approved by the courts. See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also MPEP § 2113.
With regards to claim 17, figs. 55-56 of Tsai discloses that the one or more second metal interconnects (116 above 124c) comprise a plurality of second vias (116 above 125c).
With regard to claim 18, figs. 55-56 of Tsai discloses that the first insulating layer 110 comprises: a first layer portion (110 in 306A) having a first height (height of 110 in 306A) in the second direction (bottom to top) and adjacent to the plurality of first metal interconnects (leftmost and rightmost 106) in the second direction (bottom to top); and a second layer portion (110 in 306B) having the first height (height of 110 in 306B) in the second direction (bottom to top) and adjacent to the one or more second metal interconnects (middle 106) in the second direction (bottom to top).
With regards to claim 20, figs. 55-56 of Tsai discloses that a core layer 110 adjacent to the first metallization layer 106; wherein the first metallization layer 106 is between the core layer 110 and the outer layer 124 in the second direction (bottom to top).
With regard to claim 22, figs. 55-56 of Tsai discloses that a method of fabricating an interposer substrate 100 for an integrated circuit (IC) package 300, comprising: forming a first metallization layer 106 extending in a first direction (left to right), comprising: forming a plurality of first metal interconnects (leftmost and rightmost 106); and forming one or more second metal interconnects (middle 106) each comprising a first surface (bottom of middle 106); forming an outer layer 124 adjacent to the first metallization layer 106 in a second direction (bottom to top) orthogonal to the first direction (left to right), comprising: forming an outer insulating layer 124 comprising a plurality of outer metal interconnects 126 each coupled to a first metal interconnect (leftmost and rightmost 106) of the plurality of first metal interconnects 106; and forming a die cavity 124c in at least a portion of the outer insulating layer 124 adjacent to a first surface (bottom of 106) of each of the one or more second metal interconnects (middle 106) in the second direction (bottom to top).
With regards to claim 23, figs. 55-56 of Tsai discloses forming the die cavity 124c further comprises at least partially exposing the first surface (bottom of 106 above 124c) of the one or more second metal interconnects (two middle 106).
With regards to claim 24, figs. 55-56 of Tsai discloses forming the one or more second metal interconnects (middle 106) comprises forming a metal (“copper”, par [0021]) plate.
With regards to claim 25, figs. 55-56 of Tsai discloses forming the one or more second metal interconnects (middle 106) comprises forming the one or more second metal interconnects (middle 106) co-planar with a third surface (bottom of 110) of the first metallization layer 106 adjacent to the die cavity 124c and intersecting the die cavity 124c the second direction (bottom to top).
With regards to claim 29, figs. 55-56 of Tsai discloses an integrated circuit (IC) package, comprising: a die package 306, comprising: a package substrate 306 comprising a plurality of fourth metal interconnects 310; a first die 324 coupled to the package substrate 306; and a plurality of vertical interconnects 322p each coupled to a fourth metal interconnect 310 of the plurality of fourth metal interconnects 310; and an interposer substrate 100 coupled to the die package 306 in a second direction (bottom to top) orthogonal to a first direction (left to right), the interposer substrate 100 comprising: a first metallization layer 106 extending in the first direction (left to right), the first metallization layer 106 comprising: a plurality of first metal interconnects (leftmost and rightmost 106); and one or more second metal interconnects (middle 106) each comprising a first surface (bottom of 106); an outer layer 124 coupled to the die package 306 and between the die package 306 and the first metallization layer 106 in the second direction (bottom to top), the outer layer 124 comprising: an outer insulating layer 124 comprising a plurality of outer metal interconnects 126 each coupled to a first metal interconnect (leftmost and rightmost 106) of the plurality of first metal interconnects 106 and a vertical interconnect 322p of the plurality of vertical interconnects 322p; and a die cavity 124c in at least a portion of the outer insulating layer 124 adjacent to a first surface (bottom of 106 middle 106) of each of the one or more second metal interconnects (middle 106) in the second direction (bottom to top); the first die 324 at least partially disposed in the die cavity 124c in the second direction (bottom to top).
With regard to claim 30, figs. 55-56 of Tsai discloses that the die package (306, 334) further comprises a mold layer 334 adjacent to a second surface (top of 306) of the package substrate 306 and the first die 324; wherein: the interposer substrate 100 is coupled to the mold layer 334; and the plurality of vertical interconnects 322p are disposed in the mold layer 334.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2020/0105544) in view of Kim (US 2019/0198437) (“Kim 1”).
With regards to claim 9, Tsai does not disclose that the one or more second metal interconnects at least partially intersect the die cavity in the second direction.
However, fig. 6 of Kim 1 discloses that the one or more second metal interconnects (140 in RC) at least partially intersect the die cavity RC in the second direction (top to bottom).
Therefore, it would have been obvious to one of ordinary skill in the art to form the conductive lines of Tsai with the dummy wiring layer as taught in Kim 1 in order to facilitate the dissipation of heat generated by the semiconductor chip. See par [0064] of Kim 1.
With regard to claim 21, Tsai does not disclose the interposer substrate integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable musicplayer; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
However, fig. 6 of Kim 1 discloses the interposer substrate 1000a integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer (”desktop computer”, par [0119]); a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable musicplayer; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
Therefore, it would have been obvious to one of ordinary skill in the art to integrate the package of Tsai with the desktop computer as taught in Kim in order to control the storage of memory for the desktop computer. See par [0119] of Kim 1.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2020/0105544) in view of Kim (US 2018/0240729) (“Kim 2”).
With regards to claim 19, Tsai does not disclose not comprising a core layer.
However, fig. 18 of Kim 2 discloses not comprising a core layer 300.
Therefore, it would have been obvious to one of ordinary skill in the art to form the interposer substrate of Tsai with the base substrate as taught in Kim 2 in order to provide a semiconductor package structure having a high wiring density (especially, having many input/output terminals) and improved yield. See par [0082] of Kim 2.
Allowable Subject Matter
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 26 Tsai (US 2020/0105544), Kim (US 2019/0198437) (“Kim 1”), and Kim (US 2018/0240729) (“Kim 2”) do not disclose forming the one or more second metal interconnects recessed from a third surface of the first metallization layer adjacent to the die cavity and intersecting the die cavity the second direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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