DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 6-11 in the reply filed on 8/24/2026 is acknowledged.
Claims 1-5 and 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/24/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 6-8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koduri (US 2019/0109108).
With regards to claim 6, fig. 1C of Koduri discloses a semiconductor device assembly, comprising: a substrate (“chip carrier”, par [0032]) having a first contact 118 disposed at a first side 118; a semiconductor die (“substrate 101 may be, for example, a semiconductor wafer”, par [0027]) having a second contact 103 disposed at a second side (top of 101 in fig. 1C) and corresponding to the first contact 118; and a conductive pillar 108 extending between the second contact 103 and the first contact 118 to electrically couple the substrate (“chip carrier”, par [0032]) and the semiconductor die 101, wherein the conductive pillar 108 comprises a first conductive material 111 and a portion of thermally conductive material 111 at least partially enclosed within the first conductive material 112, the thermally conductive material 111 including carbon nanotubes or graphene (“graphene”, par [0028]).
With regards to claim 7, fig. 1C of Koduri discloses that the portion of thermally conductive material 111 is tapered 113 toward the first contact 118.
With regards to claim 8, fig. 1C of Kodrui discloses that the portion of thermally conductive material 111 is covered by the first conductive material 112 at a distal portion of the conductive pillar 108 opposite the semiconductor die 101.
With regards to claim 11, fig. 1C of Kodrui discloses solder 112 disposed at a distal portion of the conductive pillar 108 opposite the semiconductor die 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri (US 2019/0109108) in view of Shin (US 2024/0234292).
With regards to claim 9, Koduri does not disclose that the portion of thermally conductive material is entirely enclosed within the first conductive material.
However, fig. 4b of Shin discloses that the portion of thermally conductive material 124 is entirely enclosed within the first conductive material 192.
Therefore, it would have been obvious to one of ordinary skill in the art to form the solder of Koduri coating around the graphene as taught in Shin in order to provide a continuous and uniform extend of solder between the substrates. See par [0039] of Shin.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri (US 2019/0109108) and Qu (US 2021/0384042).
With regard to claim 10, fig. 1C of Kodrui discloses a portion of thermally conductive material 109 at least partially enclosed within a conductive material 116.
Koduri does not disclose that the semiconductor die further includes a third contact disposed at a third side opposite the second side and a through-silicon via extending between the second contact and the third contact, the semiconductor device assembly further comprising: an additional semiconductor die having a fourth contact disposed at a fourth side and corresponding to the third contact; and an additional conductive pillar extending between the fourth contact and the third contact to electrically couple the semiconductor die and the additional semiconductor die, wherein the additional conductive pillar comprises a second conductive material.
However, fig. 1A of Qu discloses that the semiconductor die (second to bottom SD) further includes a third contact (contact at top of second to bottom SD) disposed at a third side (top of second to bottom SD) opposite the second side (bottom of second to bottom SD) and a through-silicon via T extending between the second contact (contact at bottom of second to bottom SD) and the third contact (contact at top of second to bottom SD), the semiconductor device assembly further comprising: an additional semiconductor die (third from bottom SD) having a fourth contact (bottom contact in third to bottom SD) disposed at a fourth side (bottom of third to bottom SD) and corresponding to the third contact (contact at top of second to bottom SD); and an additional conductive pillar (S, MP) extending between the fourth contact (bottom contact in third to bottom SD) and the third contact (contact at top of second to bottom SD) to electrically couple the semiconductor die (second to bottom SD) and the additional semiconductor die (third to bottom SD), wherein the additional conductive pillar (S,MP) comprises a second conductive material S.
Therefore, it would have been obvious to one of ordinary skill in the art to form the package structure of Koduri with the stacked microelectronic devices as taught in Qu in order to provide increased circuit density. See par [0023] of Koduri.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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