DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I drawn to a device and Species III of Fig. 5 drawn to claims 1-3, 6, 8-11 and 13-16 in the reply filed on 7/17/2026 is acknowledged. The traversal is on the ground(s) that Fig. 8 should not be identified as a species. This is found persuasive because the molded electronic component 100 of FIG. 3 may alternatively be the molded electronic component 100 of any of the examples described herein. Accordingly, claim 20, which is directed to the power electronics assembly illustrated in Fig. 8, will not be subject to restriction since the power electronics assembly of Fig. 8 can include any of the molded electronic components illustrated in Figs. 2-7 and identified as distinct species in the Restriction Requirement, including that of elected Species III.
Claims 4-5, 7, 12, 17-19, and 21 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/17/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 20: The claim language “a molded electronic component embedded in the printed circuit board” is interpreted by the examiner to mean that the molded electronic component 100 is encased within the printed circuit board (element 12 in Fig. 8 of the specification), this is not supported by the specification, specifically in Fig. 8, where the molded electronic component is placed on top of the printed circuit board. The examiner also notes that the term “embedded” is used in other contexts in the specification, such as the metallic body and metallic loops being at least partially embedded in the mold compound, supporting the interpretation that embedded implies within or surrounded by. A person of ordinary skill in the art would not understand how the molded compound is embedded into the printed circuit board, as it is more common practice to place the electronic device on top of the circuit board like is depicted in Fig. 8 of the instant application.
For the purposes of examination, the claim language “a molded electronic component embedded in the printed circuit board” will be interpreted by the examiner as the molded electronic component is placed on top of the printed circuit board.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 8, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kessler et al. (US 20200176412 A1) hereinafter referred to as Kessler412.
Regarding claim 1: Kesler412 teaches a molded electronic component, comprising: a mold compound (“Such an encapsulant can be, for example, a mold compound.”, para. [0030]) a die assembly comprising a semiconductor die (chip) attached to a substrate (para. [0035]), the die assembly at least partly embedded in the mold compound (“According to an aspect, a package is provided which comprises an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip”, para. [0083]); a plurality of metallic loops (contact elements) embedded in the mold compound and attached to the die assembly (“In such an embodiment, the electrically conductive protrusion may be reliably mechanically connected and electrically isolated by the same encapsulant which is also used for encapsulating the chip and part of the contact element.”, para. [0041]) and a metallic body (conductive contact structure) partly embedded in the mold compound and having a first surface that is exposed from the mold compound (“An electrically conductive contact structure 118, which is here embodied as a clip (for instance consisting of copper) provides a connection between the exposed surface 131 of the second contact structure 112 and the chip carrier 114”, para. [0103]), wherein the metallic body is attached to each of the plurality of metallic loops at a second surface of the metallic body opposite the first surface (See Fig. 16 annotated below).
Regarding claim 2: Kesler412 teaches the molded electronic component of claim 1, wherein each of the plurality of metallic loops (contact elements 108) is attached to the die assembly at a position on a contact pad of the semiconductor die (“The electrically conductive contact element 108, which is here embodied as a bimetal double layer stack, extends from (and is connected to) the pad 104.”, para. [0100]), wherein the contact pad forms a load terminal of the semiconductor die (The examiner interprets a load terminal to be any means of supplying a current to the semiconductor chip or die, such as a contact pad) and wherein the first surface of the metallic body that is exposed from the mold compound redistributes the load terminal of semiconductor die as a terminal of the molded electronic component (“Redistributes the load terminal as a terminal of the molded electronic component” is interpreted by the examiner to mean that the external contact pad on the chip or semiconductor die 104 is electrically connected to a terminal or bond pad on the surface of the die assembly 118, see Fig. 16 annotated below).
Regarding claim 3: Kesler412 teaches the molded electronic component of claim 2, wherein the metallic body has a surface area larger than that of the contact pad of the semiconductor die. (See Fig. 16 annotated below).
Regarding claim 6: Kesler412 teaches the molded electronic component of claim 1, wherein at least some of the plurality of metallic loops are shaped from discrete segments of bond wires, each segment comprising a first end and a second end that are attached to the die assembly at plurality of positions (See Fig. 16 annotated below).
Regarding claim 8: The molded electronic component of claim 1, wherein at least some of the plurality of loops are resilient. (“Furthermore, the plate-shaped geometry of the contact element has the advantage that it can be contacted in a robust manner both with the chip pad and with the electronic periphery of the package. Unlike a much more sensitive wire bond, significant pressure can be exerted on such a plate-like contact element without the risk of damaging the contact element, the electronic chip or the package.”, para. [44]).
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Fig. 16 from Kesler412 annotated: Multiple pluralities of loops are illustrated, each loop encased within the mold layer 106. Metallic bodies 118 are also shown to be partially embedded in mold layer 106.
Regarding claim 11: Kesler412 teaches the molded electronic component of claim 1, wherein the plurality of metallic loops is a first plurality of metallic loops, and wherein the molded electronic component further comprises a second plurality of metallic loops embedded in the mold compound and attached to the die assembly. (See Fig. 16 annotated above, second plurality of two loops is embedded in mold compound 106 and attached to the die assembly).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kessler et al. (US 20200176412 A1) hereinafter referred to as Kesler412 in view of Fjelstad (US 5989939) A hereinafter referred to as Fjelstad939.
Regarding claim 9: Kesler412 teaches the molded electronic component of claim 1. Kesler412 does not teach that the metallic body is attached to each of the plurality of metallic loops by one of a laser-welded joint, an adhesive, or a solder joint.
Fjelstad939 teaches covering wire bonds in a compliant layer, such as epoxy, (“Suitable compliant materials include flexiblized epoxies and silicones”, [Col 6 lines 50-55]), leaving the tops of the wire bonds exposed and connecting to connection pads using solder (“The semiconductor chip assembly of FIG. 7 can be incorporated in a larger circuit assembly by bonding the exposed top portions 11 of wire loops 9 to connection pads on an external support substrate using a plurality of joining units, such as conductive adhesive, solder, or any other suitable bonding method.”, [Col 7 lines 25-32]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that solder is well-known in the art as a method of connecting semiconductor chips to an external substrate, for instance, to incorporate the chip into a larger circuit assembly. Etching the mold layer and forming the metallic body out of solder or soldering on a contact pad, as disclosed in Fjelstad939, could be substituted into the device disclosed in Kesler412 to arrive at the claimed invention. Since the device disclosed in Fjelstad939 is substantially similar to the device disclosed Kesler412 this substitution would produce predictable results.
Regarding claim 13: Kesler412 teaches the molded electronic component of claim 11, wherein the metallic body is a first metallic body, and wherein the molded electronic component further comprises a second metallic body (See Fig. 16 annotated above, there are multiple elements 118) partly embedded in the mold compound and having a first surface that is exposed from the mold compound (See Fig. 16 annotated above, elements 118 are embedded in the mold compound 106 with top surfaces exposed).
Kesler412 does not explicitly teach wherein the second metallic body is attached to each of the second plurality of metallic loops at a second surface of the second metallic body opposite the first surface of the second metallic body.
Fjelstad939 teaches a plurality of semiconductor chips with a plurality of bond pads disposed on the surface connected to a master frame (“As depicted in FIG. 24, a plurality of semiconductor chip assemblies can be manufactured simultaneously. In such a method, a master frame 40 contains a plurality of apertures 41. Surrounding each aperture 41 is a plurality of bond pads 42 disposed on the top surface 43 of the master frame 40.”, [Col 11 lines 1-5]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor assembly may contain more than one semiconductor chip. The bond wire structure for the first plurality of loops as disclosed by Kesler412 could be manufactured in many identical chips simultaneously as taught Fjelstad939 and each chip would have its own plurality of wire loops with an identical structure a second, third, fourth, etc. See also MPEP 2144 (VI) (B), In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 14: In addition to the reasoning used to reject claim 13, Kesler412 teaches that each of the first plurality of metallic loops is attached to the die assembly at a first load terminal of the die assembly (See Fig. 16 annotated above, plurality of loops are attached to the load terminal / bond pad on top of element 1604) wherein the first surface of the first metallic body that is exposed from the mold compound redistributes the first load terminal of the die assembly as a first terminal of the molded electronic component (See Fig. 16, plurality of loops is electrically connected to metallic body 118).
Kesler412 does not teach that each of the second plurality of metallic loops is attached to the die assembly at a second load terminal of the die assembly, and wherein the first surface of the second metallic body that is exposed from the mold compound redistributes the second load terminal of the die assembly as a second terminal of the molded electronic component.
As explained in the rejection of claim 13 the structure of the second plurality of wire loops as claimed is identical to the first plurality of loops. See also MPEP 2144 (VI) (B), In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 15: In addition to the reasoning used to reject claim 14, Kesler412 teaches that the first load terminal of the die assembly is a load terminal of the semiconductor die (A “load terminal” is interpreted by the examiner to be any external contact pad on a semiconductor chip, Kesler412 teaches “Respective electrically conductive elements 108 are connected to the frontside metallization 1605 such that the frontside metallization 1605 may function as a respective pad 104.”, para. [0144])
Regarding claim 16: In addition to the reasoning used to reject claim 14, Kesler412 teaches another embodiment where a second load terminal of the die assembly is a load terminal on the substrate. (“Furthermore, it is possible to connect a wire bond as another example for an electrically conductive connection structure 118 between the functional layer 132 and an electrically conductive surface of the chip carrier 114, for instance a copper surface thereof. Thus, it is possible to use a copper wire bond for connecting the copper leadframe as chip carrier 114 with the exposed copper surface of the second contact structure 112.”, para. [0134], see Fig. 12).
Kesler412 does not teach that the second plurality of loops are all in contact with a second load terminal on the substrate in a single embodiment.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that a bond wire could be attached to the top of the device shown Fig. 16, as shown in Fig. 12 of Kessler412, to arrive at the claimed invention. The component of the bond wire and its function are known in the art and the results would be predictable.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kessler et al. (US 20200176412 A1) hereinafter referred to as Kesler412, in view of Lee et al. (US 20070222087 A1) hereinafter referred to as Lee087.
Regarding claim 10: Kesler412 teaches the molded electronic component of claim 1, Kesler412 does not teach the plurality of metallic loops is arranged in a plurality of rows of metallic loops on a surface of the die assembly.
Lee087 teaches a plurality of metallic loops arranged in a plurality of rows (“The third embodiment has both multi and single loop contacts on the source region of the die and a single gate loop contact.”, para. [0039], see also Fig. 1 multiloop contacts 104 form multiple rows). Lee also teaches the advantages of such a configuration (“Another advantage of the present invention is that the loop contacts are durable and reliable solder contacts. The prior devices, such as devices with stud balls or bumps, are susceptible to cracking “, para. [0013]).
A person of ordinary skill in the art before the effective filing date of the claimed invention, looking to improve the durability of the chip bonding structures, would have consulted the prior art to find the teachings of Kesler412 and Lee087. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that including multiple rows of loop contacts, as taught by Lee087, into the device taught by Kesler412 to arrive at the claimed invention would have a reasonable chance of further improving the bond contact reliability.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kessler et al. (US 20200176412 A1), hereinafter referred to as Kessler412, in view of Warren et al. (US 20120032350 A1) hereinafter referred to as Warren350.
Regarding claim 20: As best understood, Kesler412 teaches a power electronics assembly (Para. [0051]) comprising: a printed circuit board (“Packages may be denoted as encapsulated electronic chips with electrical connects extending out of the encapsulant and being mounted to an electronic periphery, for instance on a printed circuit board.”, para. [0003]); and an electronic device (In light of the specification a semiconductor chip is defined as an electronic device, see Fig. 16 electronic chips 102), a molded electronic component and comprising: a mold compound (“Such an encapsulant can be, for example, a mold compound.”, para. [0030]); a die assembly comprising a semiconductor die (chip) attached to a substrate (“As mentioned above, the package may comprise a chip carrier on which the electronic chip is mounted. For instance, such a chip carrier may comprise a leadframe and/or a ceramic sheet (or another electrically insulating body made of another material such as silicon nitride or aluminum oxide) covered on both opposing main surfaces with a respective metallic layer (in particular an Active Metal Braze (AMB) substrate and/or a Direct Copper Bonding (DCB) substrate). Thus, a proper mounting base for mounting the chip can be established.”, para. [0035]), the die assembly at least partly embedded in the mold compound (“According to an aspect, a package is provided which comprises an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip”, para. [0083]); a plurality of metallic loops (contact elements) embedded in the mold compound and attached to the die assembly (para. [0034]) (“In an embodiment, the at least one electrically conductive protrusion extends through the encapsulant so as to be exposed with respect to the encapsulant. In such an embodiment, the electrically conductive protrusion may be reliably mechanically connected and electrically isolated by the same encapsulant which is also used for encapsulating the chip and part of the contact element. The result is a compact and reliable package.”, para. [0041]); and a metallic body (conductive contact structure) partly embedded in the mold compound and having a first surface that is exposed from the mold compound (See Fig. 16 annotated above), wherein the metallic body is attached to each of the plurality of metallic loops contact at a second surface of the metallic body opposite the first surface (See Fig. 16 annotated above).
Kesler412 does not teach that the electronic device is electrically connected to the molded electronic component through the printed circuit board, or explicitly show that the molded electronic device is embedded in (on top of) the printed circuit board.
Warren305 teaches a method for mounting an electronic component (die 102) so that electrical signals may be passed through a circuit board (“In the BGA packaging, solder pads represent a type of interface pad. Some interface pads such as solder pad 118 are electrically coupled to a metal trace in the printed circuit board where electronic signals or electricity can pass between die 102 and other components. Other interface pads are sometimes used to thermally couple the package to the printed circuit board.”, para. [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that an electronic device, such as a semiconductor chip or die, could be soldered to a circuit board to share electrical signals or electricity between devices on the circuit board, as taught by Warren305, including to a molded electronic component as disclosed Kesler412. The substituted components of solder connections to the circuit board and their function are both well-known in the art and the results of their substitution would have predictable results.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Nikitin et al. (US 20220352114 A1) teaches a semiconductor chip on a circuit board with wire bonds encased in a mold compound and electrical connections to the wire bonds on top of the mold compound.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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