Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's amendment/arguments filed on 3/23/26 as being acknowledged and entered. By this amendment claims 1-2, 4-5, and 7-20 are pending and claims 3 and 6 are cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyata et al. (US Patent 9,449,987).
Claim 1: Miyata teaches (Fig. 26B, 29C) an integrated circuit device, comprising: a substrate having a cell region (100) and a dummy region (300) surrounding the cell region; a cell stack structure including a plurality of insulating layers (32, 232) and a plurality of conductive layers (46, 246) alternately stacked on the cell region of the substrate; a dummy stack (301A, 301B) structure including a plurality of dummy insulating layers (32, 232) and a plurality of dummy support layers (42, 242) alternately stacked on the dummy region of the substrate; a plurality of channel structures (55/60) penetrating the cell stack structure, each channel structure of the plurality of channel structures including a respective upper portion and a respective lower portion (fig 26); and a filling structure (36) penetrating the dummy stack structure, the filling structure (65, 265) surrounding the cell stack structure and the plurality of channel structures, the filling structure including a first filling part (110) at a same level as the lower portion of each channel structure of the plurality of channel structures and a second filling part (210) at a same level as the upper portion of each channel structure of the plurality of channel structures, wherein a level of a bottom surface of the filling structure is substantially equal to a level of a bottom surface of each of the plurality of channel structures, wherein the dummy stack structure includes a lower dummy portion at the same level as the lower portion of each channel of the plurality of channel structures and an upper dummy portion on the lower dummy portion, wherein the upper dummy portion is at the same level as the upper portion of each channel structure of the plurality of channel structures, wherein the lower dummy portion has a lower slit, wherein the upper dummy portion has an upper slit, wherein the first filling part extends through the lower dummy portion and fills the lower slit, and wherein the second filling part extends through the upper dummy portion and fills the upper slit (Fig. 28A-D) (Col. 33 lines 45-62, Col. 34 lines 4-23).
Claim 2: Miyata teaches (Fig. 26B, 29C) a level of a top surface of the filling structure (36,37) is substantially equal to a level of a top surface of each of the plurality of channel structures.
Claim 4: Miyata teaches (Fig. 26B, 28D, 29C) a maximum width of the first filling part is greater than a minimum width of the second filling part.
Claim 5: Miyata teaches (Fig. 26B, 29C) the second filling part overlaps with the first filling part.
Claim 7: Miyata teaches (Fig. 26B, 29C) the upper dummy portion overlaps with the lower dummy portion.
Claim 8: Miyata teaches (Fig. 26B, 29C) the dummy stack structure surrounds the cell stack structure.
Claim 9: Miyata teaches (Fig. 26B, 29C) each the plurality of channel structures is connected to a portion of the cell region of the substrate; and the filling structure is connected to a portion of the dummy region of the substrate.
Claim 11: Miyata teaches (Fig. 26B, 29C) each of plurality of dummy support layers includes a different insulating material from each of the plurality of dummy insulating layers (Col. 6-7).
Claim 12: Miyata teaches (Fig. 26B, 29C) a number of the plurality of conductive layers is the same as a number of the plurality of dummy support layers.
Claim 13: Miyata teaches an integrated circuit device (Fig. 26B, 29C) comprising: a substrate having a cell region (100) and a dummy region (200) surrounding the cell region; a cell stack structure (1000, 2000) including a plurality of insulating layers (232) and a plurality of word line structures (246) alternately stacked on the cell region of the substrate; a dummy filling structure surrounding the cell stack structure, the dummy filling structure including a first filling layer (110) and a second filling layer (210) on the first filing layer; a plurality of channel structures (55) penetrating the cell stack structure; and a first dummy stack structure (bottom section of 301A) penetrating the first filling layer, the first dummy stack structure surrounding the cell stack structure and the plurality of channel structures on the dummy region of the substrate, wherein a level of a bottom surface of the first dummy stack structure is substantially equal to a level of a bottom surface of each of the plurality of channel structures, wherein the first dummy stack structure includes a slit, and wherein the first filling layer fills the slit (Fig. 28A-D) (Col. 33 lines 45-62, Col. 34 lines 4-23).
Claim 14: Miyata teaches (Fig. 23, 26B) a second dummy stack structure (top section of 301A) penetrating an upper portion of the dummy filling structure, wherein the second dummy stack structure overlaps with the first dummy stack structure.
Claim 15: Miyata teaches (Fig. 23, 26B) a second dummy stack structure (210) the second dummy stack structure surrounds the cell stack structure and the plurality of channel structures.
Claim 16: Miyata teaches (Fig. 23, 26B) a second dummy stack structure (210) the first filling layer includes insulating material (Col. 10).
Claim 17: Miyata teaches (Fig. 23, 26B) a top surface of the second dummy stack structure is substantially equal to a level of a top surface of each of the plurality of channel structures.
Claim 18: Miyata teaches (Fig. 23, 26B) the second filling layer includes insulating material (Col. 22).
Claim 19: Miyata teaches (Fig. 23, 26B) the second filling layer overlaps with the first filling layer.
Claim 20: Miyata teaches (Fig. 23, 26B) each of the first dummy stack structure and the second guard structure has a sloped profile along an edge.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US PGPub 2021/0028104).
Claim 1: Lee teaches (Fig. 3B-4B) an integrated circuit device, comprising: a substrate having a cell region (CNA) and a dummy region (DM) surrounding the cell region; a cell stack structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked on the cell region of the substrate [0070]; a dummy stack (DM) structure including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked on the dummy region of the substrate; a plurality of channel structures [0022] penetrating the cell stack structure, each channel structure of the plurality of channel structures including a respective upper portion and a respective lower portion; and a filling structure [0093] penetrating the dummy stack structure, the filling structure surrounding the cell stack structure and the plurality of channel structures, the filling structure including a first filling part at a same level as the lower portion of each channel structure of the plurality of channel structures and a second filling part (at a same level as the upper portion of each channel structure of the plurality of channel structures, wherein a level of a bottom surface of the filling structure is substantially equal to a level of a bottom surface of each of the plurality of channel structures, wherein the dummy stack structure includes a lower dummy portion at the same level as the lower portion of each channel of the plurality of channel structures and an upper dummy portion on the lower dummy portion, wherein the upper dummy portion is at the same level as the upper portion of each channel structure of the plurality of channel structures, wherein the lower dummy portion has a lower slit, wherein the upper dummy portion has an upper slit, wherein the first filling part extends through the lower dummy portion and fills the lower slit, and wherein the second filling part extends through the upper dummy portion and fills the upper slit. The first a second filling parts can be the bottom and top halves of the same filling structure.
Claim 13: Lee teaches (Fig. 3B-4B) (see claim 1) an integrated circuit device comprising: a substrate having a cell region and a dummy region surrounding the cell region; a cell stack structure including a plurality of insulating layers and a plurality of word line structures alternately stacked on the cell region of the substrate; a dummy filling structure surrounding the cell stack structure, the dummy filling structure including a first filling layer and a second filling layer on the first filing layer; a plurality of channel structures penetrating the cell stack structure; and a first dummy stack structure penetrating the first filling layer, the first dummy stack structure surrounding the cell stack structure and the plurality of channel structures on the dummy region of the substrate, wherein a level of a bottom surface of the first dummy stack structure is substantially equal to a level of a bottom surface of each of the plurality of channel structures, wherein the first dummy stack structure includes a slit, and wherein the first filling layer fills the slit.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4-5, and 7-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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