Prosecution Insights
Last updated: July 17, 2026
Application No. 18/605,325

LIGHT RECEIVING ELEMENT

Non-Final OA §102
Filed
Mar 14, 2024
Priority
Mar 15, 2023 — JP 2023-040426
Examiner
AU, BAC H
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Aio Core Co. Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
673 granted / 832 resolved
+12.9% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
861
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
80.8%
+40.8% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
1.5%
-38.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 832 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Usami (U.S. Pub. 2017/0317221). Regarding claims 1-6, Usami [Figs.20,22] discloses a light receiving element comprising: a first semiconductor layer [SL], the first semiconductor layer formed on a substrate or constituting a part of the substrate [1S]; a light absorbing layer [IGL] formed on the first semiconductor layer; and a second semiconductor layer [NGL] formed on the light absorbing layer; wherein the first semiconductor layer comprises plural regions having film thicknesses that are different from one another [Thinner center region]; wherein the number of the plural regions in the first semiconductor layer is equal to or greater than 3 [2 side regions and 1 center region]; wherein the first semiconductor layer [SL] is formed on a first dielectric layer [BOX]; further comprising a second dielectric layer [IL] on the second semiconductor layer; wherein the first dielectric layer [BOX] is a buried oxide film in an SOI substrate, and the first semiconductor layer [SL] is an Si thin film on the buried oxide film in the SOI substrate [1S]; wherein the light absorbing layer is a layer [IGL] comprising Ge [Para.42]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAC H AU/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 14, 2024
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME
2y 10m to grant Granted Jun 23, 2026
Patent 12660448
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2y 7m to grant Granted Jun 16, 2026
Patent 12649668
METAL OXIDE NANOPARTICLE, NANOCOMPOSITE INCLUDING THE METAL OXIDE NANOPARTICLE, AND INK COMPOSITION, LIGHT-EMITTING DEVICE, ELECTRONIC APPARATUS, AND ELECTRONIC EQUIPMENT INCLUDING THE NANOCOMPOSITE
2y 6m to grant Granted Jun 09, 2026
Patent 12652789
SEMICONDUCTOR DEVICES HAVING LANDING PAD STRUCTURES
2y 6m to grant Granted Jun 09, 2026
Patent 12648160
SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC STRUCTURE AND METHOD FOR FORMING THE SAME
2y 6m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
92%
With Interview (+11.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 832 resolved cases by this examiner. Grant probability derived from career allowance rate.

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