Prosecution Insights
Last updated: October 02, 2026
Application No. 18/605,344

METHOD AND APPARATUS FOR ELECTRICAL BOND PROTECTION

Non-Final OA §103
Filed
Mar 14, 2024
Examiner
RODELA, EDUARDO A
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lumileds LLC
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
932 granted / 1080 resolved
+18.3% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
27 currently pending
Career history
1099
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
18.3%
-21.7% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1080 resolved cases

Office Action

§103
DETAILED ACTION This correspondence is in response to the communications received March 14, 2024. Claims 1-7 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I (claims 1-7) in the reply filed on August 20, 2026 is acknowledged. Claims 8-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II and III claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 20, 2026. Relevant Prior Art Heffels et al. (US 2023/0304655) Fig. 2c, shown below. PNG media_image1.png 450 630 media_image1.png Greyscale Glob top. Rantala (US 2015/0243852) Fig. 5a, shown below. PNG media_image2.png 400 446 media_image2.png Greyscale Glob top teaching. Lai (US 2011/0248616) Fig. 5, shown below. PNG media_image3.png 484 628 media_image3.png Greyscale BRI, Chen et al. (US 2010/0207142) Fig. 2B, shown below. PNG media_image4.png 546 386 media_image4.png Greyscale BRI, Sanpei et al. (US 2008/0128739) Fig. 7, shown below. PNG media_image5.png 420 672 media_image5.png Greyscale Applicant’s Claim to Figure Comparison It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant. PNG media_image6.png 386 584 media_image6.png Greyscale Regarding claim 1, the Applicant discloses in Fig. 1, a method for forming a light emitting device, the method comprising: attaching a printed circuit board (140) to a heat sink (120); attaching a top contact light emitting diode (LED) (160) to the heat sink (120); and electrically coupling the printed circuit board (140) to the top contact LED (160) via conductive elements (180). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,433,086 used for translation of WO2023/182853, which has publish date of September 28, 2023) in view of Liao et al. (US 2011/0157897). PNG media_image7.png 744 764 media_image7.png Greyscale PNG media_image8.png 602 782 media_image8.png Greyscale PNG media_image9.png 456 816 media_image9.png Greyscale Regarding claim 1, the prior art of Lee discloses in Figs. 1-4, a method for forming a light emitting device (see title, “Lighting module and lighting device”), the method comprising: attaching a printed circuit board (“circuit board 110”, col. 5, line 53. The term “printed” will be addressed in the combination rejection below.) to a heat sink (“heat dissipation plate 101”, col. 5, line 53. The term “heat sink” is satisfied by the “heat dissipation plate”, as both elements direct excess heat away from the active device to maintain a desired lower level of temperature during operation of the active device. Element 110 shown attached to 101.); attaching a top contact light emitting diode (LED) (Interpreted to be element 130, where, “The light source portion 130 may be a lighting module having a single LED chip or multiple LED chips and a wavelength conversion layer.”, col. 5, lines 60-62. As can be seen in Figs. 1-3, the 130 has “top contacts” where wirings connect thereto, “connection member 141 and 142 connecting the light source portion 130 and the circuit board 110”, col. 5, lines 56-58) to the heat sink (130 attached directly to the top surface of 101, see at least Fig. 3. Element 130 shown attached to 101.); and electrically coupling the printed circuit board (110) to the top contact LED (130) via conductive elements (“connection member 141 and 142 connecting the light source portion 130 and the circuit board 110”, col. 5, lines 56-58, further, “The first and second bonding pads 134 and 135 may be electrically connected to the circuit board 110 through a connection member 141 and 142.”, col. 8, lines 64-67). Lee does not specify wherein the circuit board is a “a printed circuit board”. PNG media_image10.png 326 738 media_image10.png Greyscale Liao teaches a similar arrangement, where a circuit board is used for electrical connections, and the circuit board is referred to as “the printed circuit board 22”, ¶ 0044. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the feature of, a circuit board which is a “a printed circuit board”, as disclosed by Liao in the system of Lee, for the purpose of utilizing a circuit redistribution element which can be easily fabricated with a printing patterning process, which can be premade and prechecked to be sure to eliminate a point of failure in the overall fabrication process of the “method for forming a light emitting device”. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Regarding claim 4, the prior art of Lee et al. disclose the method of claim 1, and Lee discloses in Figs. 1-4, wherein the conductive elements (“connection member 141 and 142 connecting the light source portion 130 and the circuit board 110”, col. 5, lines 56-58) include one or more downward-bent wires (shown are two “downward bent” wires 141 and 142, where the bend faces down ward.). Regarding claim 6, the prior art of Lee et al. disclose the method of claim 1, and Lee discloses in Fig. 1-4, further comprising: PNG media_image11.png 552 720 media_image11.png Greyscale forming a hole (Portion 108, “The heat dissipation plate 101 includes a heat dissipation portion 102 and a side portion 103, and the heat dissipation portion 102 may include a substrate heat dissipation portion 102A having a recess portion 108 into which the circuit board 110 is inserted.”, col. 6, lines 9-14) in the heat sink (“heat dissipation plate 101”, col. 6, line 9), wherein the printed circuit board (110, col. 6, line 14, where the “printed” aspect addressed in the rejection of claim 1) and the top contact LED (130, col. 5, lines 60-62) are located on opposite sides of the hole (108) and the conductive elements span the hole (141/142, col. 8, lines 64-67, span 108, and 130 is on opposite side of 108 to 110). Regarding claim 7, the prior art of Lee et al. disclose the method of claim 1, and Lee discloses in Figs. 1-4, wherein the top contact LED (130, col. 5, lines 60-62) is attached to the heat sink (101/102, col. 6, lines 9-14) at a point that is higher than a location where the printed circuit board is attached (board 110 is attached to low point 102A of 101 in recess/hole 108, which is lower than where LED 130 is attached at 102 of 101, see Fig. 4). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,433,086 used for translation of WO2023/182853, which has publish date of September 28, 2023) in view of Liao et al. (US 2011/0157897) in view of Lai (US 2011/0175512) in view of Lee et al. (US 2005/0199884, hereinafter referred to as the ‘884 reference’). Regarding claim 2, the prior art of Lee et al. disclose the method of claim 1, however Lee does not disclose, “further comprising: encapsulating the conductive elements by applying an adhesive glob top.” PNG media_image12.png 492 624 media_image12.png Greyscale Lai discloses in Fig. 1, further comprising: encapsulating the conductive elements (analogous conductive elements are wire bonds 18, ¶ 0018) by applying an adhesive glob top (“The encapsulation layer 19 is configured for optically adjusting (e.g., diverging or converging) a direction of the light emitted from the LED chip 12, thus adjusting an illuminating scope of the LED 10. In addition, the encapsulation layer 19 protects the LED chip 12 from contaminants.”, ¶ 0019). It is understood that the “encapsulation layer 19” of Lai is itself an “adhesive”, since it is a clear material that was applied to surround all surfaces it was applied to, however just to explicitly show this is the case, the ‘884 reference is brought in to show this, where in ¶ 0061, “the encapsulant 610 forming the package body and the lens 612 are made of resins preferably having strong adhesive force in order to fixedly secure the underlying first and second lead frames 604 and 606 in the bottom thereof while sealing the LED chip 602 therein.”, of Fig. 19, shown below. PNG media_image13.png 198 480 media_image13.png Greyscale Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the feature of, “further comprising: encapsulating the conductive elements by applying an adhesive glob top”, as disclosed by Lai and the ‘884 reference in the system of Lee, for the purpose of utilizing a transparent covering which can protect the delicate light emitting device and its electrical connections from mechanical damage and from environmental degrading exposure, further shape of the encapsulant can aid in directing light in a uniform manner outwardly. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,433,086 used for translation of WO2023/182853, which has publish date of September 28, 2023) in view of Liao et al. (US 2011/0157897) in view of Lai (US 2011/0175512). Regarding claim 3, the prior art of Lee et al. disclose the method of claim 1, however Lee does not disclose, “further comprising: applying a conformal coating to the conductive elements, wherein the conformal coating isolates the conductive elements.” PNG media_image12.png 492 624 media_image12.png Greyscale Lai discloses in Fig. 1, further comprising: applying a conformal coating (“The encapsulation layer 19 is disposed on the LED chip 12, to cover the LED chip 12, as well as part of the positive electrode 17a, part of the negative electrode 17b, and the two wires 18.”, ¶ 0018) to the conductive elements (“two wires 18”, ¶ 0018. The term “conformal” has been interpreted in the manner supplied by the Applicant, where as can be seen in Applicant’s Fig. 2, element 290 “conformally” coats the entirety of the wires 280, such that the entirety of the outer surfaces of 280 are coated, which is literal application of the term “conformal”, where 290 conforms fully to surfaces of 280.), wherein the conformal coating isolates the conductive elements (wires 18 are fully isolated from the external environment and each other by the coating of 19). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the feature of, “further comprising: applying a conformal coating to the conductive elements, wherein the conformal coating isolates the conductive elements.”, as disclosed by Lai in the system of Lee, for the purpose of utilizing a protective covering which can protect the delicate electrical connections from mechanical damage and from environmental degrading exposure which could oxidize and degrade the function of the wires over time. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,433,086 used for translation of WO2023/182853, which has publish date of September 28, 2023) in view of Liao et al. (US 2011/0157897) in view of Lamson et al. (US 6,822,340). Regarding claim 3, the prior art of Lee et al. disclose the method of claim 1, however Lee does not disclose, “further comprising: applying a conformal coating to the conductive elements, wherein the conformal coating isolates the conductive elements.” PNG media_image14.png 372 528 media_image14.png Greyscale Lamson discloses in Fig. 4a, further comprising: applying a conformal coating (“low dielectric constant sheath 45 conforming to the wire.”, col. 4, lines 35-40) to the conductive elements (“wire 41”, col. 4, line 36), wherein the conformal coating isolates the conductive elements (“wire shorting is eliminated”, col. 5, line 39). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the feature of, “further comprising: applying a conformal coating to the conductive elements, wherein the conformal coating isolates the conductive elements”, as disclosed by Lamson in the system of Lee, for the purpose of utilizing a protective covering which can protect the delicate electrical connections from mechanical damage and from environmental degrading exposure which could oxidize and degrade the function of the wires over time. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Regarding claim 5, the prior art of Lee et al. disclose the method of claim 1, however Lee does not disclose, “wherein the conductive elements include one or more upward-bent wires.” conductive elements.” PNG media_image14.png 372 528 media_image14.png Greyscale Lamson discloses in Fig. 4a, further comprising: wherein the conductive elements (“wire 41”, col. 4, line 36) include one or more upward-bent wires (the left most bend in wire 41 has a curvature that is more “upward”). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the feature of, “wherein the conductive elements include one or more upward-bent wires”, as disclosed by Lamson in the system of Lee, for the purpose of utilizing a wire geometry that has less height, which can lower the profile of the overall circuit construction which can increase form factor minimization and device compatibility. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDUARDO A RODELA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Mar 14, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.7%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1080 resolved cases by this examiner. Grant probability derived from career allowance rate.

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