SEMICONDUCTOR PACKAGE

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed 8/28/2026 has been entered. Claims 1-5 and 7-20 remain pending in the application. Response to Arguments Applicant's arguments with respect to Claim 1 have been fully considered but they are not persuasive. Regarding Claim 1, Applicant argues that Examiner’s “rationale is textbook hindsight reasoning from Applicant’s own disclosure, and this rationale is unsupported by the cited references.” (Applicant’s Remarks, filed 8/28/2026, pg. 9.) Applicant further states that the only mention of structural stability is applicant’s own specification, in Paragraphs [0004] and [0043]. However, while the words stability overlap, the rest of the rationale is distinct from Applicant’s disclosure. In Para. [0043], Applicant provides a discussion for the motivation of adding a connection substrate. That Paragraph states “The first logic chip 300 may be buried in the first molding layer 400 and the connection substrate 200, thereby being protected. In other words, the first molding layer 400 and the connection substrate 200 may protect the first logic chip 300 from external impacts. Thus, because the first logic chip 300 is not exposed to external impact, the semiconductor package 10 may increase in reliability and structural stability.” (Bold added by Examiner for emphasis). From this Paragraph, particularly the bolded statements, Applicant’s reason for adding the connection substrate is to protect the first logic chip from the external environment, and this increases reliability and structural stability. So, the structural stability being discussed is the stability of the first logic chip, since that is what is being protected. In contrast, in Examiner’s rejection, Examiner states “Also, it would have been obvious to modify H. Lee by adding the connection substrate of Meyer above the first redistribution layer. Doing so would have the advantage of adding stability and firmness to that layer, making it easier to add another layer on top.” (Bold added by Examiner for emphasis). Thus, although word “stability” appears in both places, it pertains to two different structures. In Applicant’s specification, Applicant is trying to protect the first logic chip from the external environment, thus increasing its reliability and stability. In Examiner’s rationale, Examiner is discussing the stability of the connection layer, and stating that adding this layer would make it easier to add another layer on top. Although this rationale does not appear in H. Lee, Examiner may adduce a rationale from basic scientific reasoning (MPEP 2144 I). Thus, Examiner is maintaining the rejection of Claim 1 (and claims 2-4) on the same grounds as before. Regarding Claim 5 and 11, Examiner finds Applicant’s arguments persuasive. Thus, Examiner is withdrawing the rejections of those claims and the claims dependent therefrom. Claim Rejections - 35 USC § 103 Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over US20210358875A1 (H. Lee) in view of US20220262777A1 (D. Lee) and US20180315737A1 (Meyer). Regarding Claim 1 and 4, H. Lee discloses a semiconductor package (Fig. 1, el. 100, Para. [0036]) comprising a logic structure (Para. [0043] – which discloses that the semiconductor devices 142 and 152 can be logic devices), wherein the logic structure includes: a first redistribution substrate (Fig. 1, el. 130, Para. [0036]); a plurality of connection members (Fig. 1, el. CP, Para. [0036] – the molding layer on the redistribution) on the first redistribution substrate (Fig. 1), a first logic chip (Fig. 1, el. 140, Para. [0043]) on the first redistribution substrate and in the opening in the connection substrate (Fig. 1); and a second logic chip (Fig. 1, el. 150, Para. [0043]) on the first logic chip (Fig. 1, Para. [0036]), wherein a first active surface of the first logic chip faces a second active surface of the second logic chip (Para. [0041]). H. Lee does not disclose a lower redistribution substrate; a logic structure on the lower redistribution substrate; a plurality of connection terminals between the lower redistribution substrate and the logic structure; a plurality of connection structures on the lower redistribution substrate, the plurality of connection structures surrounding the logic structure in plan view; and a plurality of external connection terminals below the lower redistribution substrate. H. Lee does not disclose a connection substrate on the first redistribution substrate, the connection substrate having an opening in the connection substrate. H. Lee also does not disclose an upper redistribution substrate on the plurality of connection structures and on the logic structure; and a memory chip on the upper redistribution substrate, wherein the plurality of connection structures electrically connect the lower redistribution substrate to the upper redistribution substrate. D. Lee discloses a semiconductor package (Fig. 1, Para. [0018]) comprising: a lower redistribution substrate (Fig. 1, el. 500, Para. [0045]); a logic chip (Fig. 1, el. 600, Para. [0051]) on the lower redistribution substrate (Fig. 1, Para. [0051]); a plurality of connection structures (Fig. 1, el. 440, Para. [0059]) on the lower redistribution substrate (Para. [0059]), the plurality of connection structures surrounding the logic structure in plan view (Fig. 1, Para. [0059]); and a plurality of external connection terminals below the lower redistribution substrate (Fig. 1, el. 522, Para. [0045]). D. Lee further discloses an upper redistribution substrate (Fig. 6, el. 700, Para. [0060]) on the plurality of connection structures and on the logic structure (Fig. 6); and a memory chip (Fig. 6, el. 820, Para. [0090]) on the upper redistribution substrate (Fig. 6), wherein the plurality of connection structures electrically connect the lower redistribution substrate to the upper redistribution substrate (Paras. [0059 and 0062]). Meyer discloses a semiconductor package (Fig. 1, el. 102, Para. [0021]) with a connection substrate (Fig. 1, el. 118, Para. [0022]) on a first redistribution substrate (Fig. 1, el. 112, Para. [0024]), the connection substrate having an opening in the connection substrate (Fig. 1); a first logic chip in the opening of the connection substrate (Fig. 1 el. 106, Para. [0020]); a first molding layer that covers the connection substrate (Fig. 1, el. 104, Para. [0021]), wherein the first molding layer extends into a gap between the connection substrate and the first logic chip (Fig. 1). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add the structure of D. Lee, including the memory device, around the logic structure of H. Lee to create a more complex device. As disclosed by D. Lee, this kind of package around a logic structure has the benefit of using a package on package technique to vertically stack semiconductor chips to create a high-density chip stack (Para. [0004]). Also, it would have been obvious to modify H. Lee by adding the connection substrate of Meyer above the first redistribution layer. Doing so would have the advantage of adding stability and firmness to that layer, making it easier to add another layer on top. 14. Regarding Claim 2, H. Lee in view of D. Lee discloses the semiconductor package of claim 1, wherein a size in a first direction of the second logic chip is greater than a size in the first direction of the first logic chip (Fig. 1, where el. 150 is wider than el. 140). 15. Regarding Claim 3, H. Lee in view of D. Lee discloses the semiconductor package of claim 1, wherein the first logic chip includes a plurality of through vias (Fig. 1, el. 145, Para. [0044] that electrically connect the first active surface of the first logic chip to a first inactive surface of the first logic chip that is opposite to the first active surface (Paras. [0045 and 0046]). Allowable Subject Matter Claims 5 and 7-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 5 and 7-10, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination “wherein a roughness of a surface of the first molding layer is greater than a roughness of a surface of the dielectric pattern.” Regarding Claims 11-20, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination “wherein a width of the connection via increases with the increasing distance from the bottom surface of the first redistribution surface.” Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899