Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 20, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 has been entered.
Response to Amendment
The Amendment filed June 2, 2026 has been entered. Claims 1, 3-15, & 17-20 remain pending in the application. Claims 1, 11, & 13 have been amended. Applicant’s amendments to the Claims have overcome each and every 112(a) rejection previously set forth in the Final Office Action mailed April 7, 2026, hereafter referred to as the Final Office Action.
Response to Arguments
Applicant’s arguments, see pp. 10-13 of Applicant remarks, filed June 2, 2026, with respect to the rejection(s) of claim(s) 1, 3, 7, & 9-10 under U.S.C. § 103 have been fully considered but they are not persuasive. Applicant in their submitted response has presented the argument that the references, Nishimura (US 2017/0271452A1), in view of Shimada (US 2009/0261861), and further in view of Ito et al. (US 2021/0048472 A1), do not teach, suggest, or disclose all the limitations currently recited in independent claim 1, “ an electrode evaluation unit that evaluates the upper-surface electrode of the main element based on a deviation between an initial value of the sense ratio and the sense ratio measured by the sense ratio measurement unit, wherein the electrode evaluation unit determines that the upper-surface electrode has degraded if the deviation is equal to or greater than a reference value.”
The Examiner respectfully disagrees based on two reasonings. First, while the Applicant correctly notes that Ito generally refers to detecting the deterioration of the “bonding wire,” Ito defines this deterioration as occurring at the surface electrode itself. Ito states this configuration detects a case where a bonding wire is “broken off from the semiconductor die device by the development of a crack near the interface between the bonding wire and the surface electrode” ([0029]). Under BRI, a unit that detects a crack at the interface of the surface electrode is inherently evaluating the structural and electrical integrity of the upper-surface electrode. Please refer to MPEP 2103, 2111, 211.01, & 2173.02. The upper-surface electrode and the bonding wire form a single electrical node; detecting a failure at their physical interface constitutes evaluating the electrode’s condition. Second reason, is that the bonding wire and the upper-surface electrode are mechanically and electrically coupled components subject to the same thermal stresses and current loads. A POSITA would find it obvious to apply Ito’s method of evaluating degradation (via comparing sense rations against a reference value) to the upper-surface electrode itself. The motivation would be to ensure the reliability of the entire connection node, as degradation in either the wire or the electrode surface would yield the same predictable change in electrical inductance/resistance. Please refer to MPEP 2123, 2143.01(I), 2143.02, & 2144.04.
Applicant’s arguments, see pp. 11-13 of Applicant remarks, filed June 2, 2026, with respect to the rejection(s) of claim(s) 11-12, 14-15, & 20, under U.S.C. § 103 have been fully considered but they are not persuasive. Applicant in their submitted response has presented the argument that the references, Nishimura (US 2017/0271452A1), in view of Hideshi (JP 2010199279 A), in view of Shimada (US 2009/0261861), in view of Ito et al. (US 2021/0048472 A1), and further in view of Sugiyama (US 2023/029087 A1), do not teach, suggest, or disclose all the limitations currently recited in independent claim 11, stating “The Examiner does not explain the role of Ito in the rejection of claim 11 for no apparent reason,” and “Claim 11 as amended requires first and second sense wiring lines that both correspond to the same sensing element…the applied combination of references applied in the rejection of claim 11 cannot render amended claim 11 obvious.”
The argument is persuasive in part, and the Examiner agrees that the teachings of Ito are not required to meet the limitations of independent claim 11. Accordingly, to clarify the record, the rejection of claim 11 has been modified to withdraw Ito. The updated rejection of claim 11 is now maintained solely over the combination of Nishimura, Shimada, and Sugiyama.
In response to applicant's argument that amended claim 11 requires both the first and second sense wiring lines to correspond to the same current sensing element, whereas Sugiyama discloses each sense electrode corresponding to a different sensing element, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The Applicant’s argument inappropriately relies on “bodily incorporation.” Please see MPEP 2144.04, 2145(IV), and 2145(V), the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference, nor is it whether the claimed invention is expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have predictably suggested to a person of ordinary skill in the art.
The second reason the Examiner would like to highlight is that in the present rejection, Shimada is relied upon to provide the single claimed “current sensing element” (e.g., sense MOSFET 2) and the circuit portion connected to a ground potential ([0004]-[0005], [0007], & [0044]-[0048]). Nishimura is relied upon to provide the primary physical upper-surface electrode and the first sense wiring line (Figs. 1 & 2; [0006], [0034]-[0037], [0039]-[0040], [0042], [0046]-[0047], [0057]-[0067], & [0100]). Sugiyama is relied upon solely for teaching the utilization of a dual-line sensing layout, specifically, adding a second sense wiring line (e.g., the second Kelvin terminal) to isolate the sensing ground loop from the gate control loop and shield micro sense voltages (Fig. 4; [0029]-[0031] & [0040]-[0041]). When modifying the Nishimura-Shimada device to include the noise-shielding benefits taught by Sugiyama, it would have been obvious to a POSITA to route both the firs sense wiring line and the newly added second sense wiring line to the same circuit portion of the same single sensing element taught by Shimada. The fact that Sugiyama’s chip utilizes multiple sensing elements across its die does not negate the obviousness of extracting Sugiyama’s dual-wire isolation technique and applying it to the single sensing element architecture provided by Shimada. Doing so is a substitution and predictable variation of known techniques to improve the accuracy and stability of the current sense monitoring loop.
Applicant’s arguments, see pg. 13 of Applicant remarks, filed June 2, 2026, with respect to the rejection(s) of claim(s) 12, 14-15, & 13, under U.S.C. § 103 have been fully considered but they are not persuasive. Applicant in their submitted response has presented the argument that the references, Nishimura (US 2017/0271452A1), in view of Hideshi (JP 2010199279 A), in view of Shimada (US 2009/0261861), in view of Ito (US 2021/0048472 A1), and further in view of Sugiyama (US 2023/029087 A1), for claims 12 & 14-15, and Nishimura (US 2017/0271452A1), in view of Hideshi (JP 2010199279 A), in view of Shimada (US 2009/0261861), in view of Ito (US 2021/0048472 A1), in view of Sugiyama (US 2023/029087 A1), and further in view of Fukuhara (US 2022/0029410 A1), for claim 13, are allowable because they depend from claim 11, and do not teach, suggest, or disclose all the limitations currently recited in independent claim 11, stating “the applied art cannot render claims 12 and 14-15 obvious for the same reasons as provided above for claim 11,” and “Fukuhara does nothing to remedy the defects noted with respect to the rejection of claim 11.”
The Examiner respectfully disagrees based on two reasonings. First, because the rejection of claim 11 has been maintained, please see updated rejection below and explanation above, the argument is not persuasive. Therefore the rejections of claims 12 and 14-15 are maintained.
Secondly, the Applicant argues that the rejection of dependent claim 13 over the combination of Nishimura, Hideshi, Shimada, Sugiyama, and Fukuhara should be withdrawn because Fukuhara does not remedy the defects in base claim 11. As noted above, the rejection of base claim 11 is properly maintained. Furthermore, Fukuhara teaches the claimed selector mechanism applied to the circuit portion ([0044], [0052], & [0054). The Applicant has not independently traversed the merits of Fukuhara’s mapping, therefore the rejection of claim 13 is maintained.
Applicant’s arguments, see pg. 13 of Applicant remarks, filed June 2, 2026, with respect to the rejection(s) of claim(s) 20 under U.S.C. § 103 have been fully considered but they are not persuasive. Applicant in their submitted response has presented the argument that the references, Nishimura (US 2017/0271452A1), in view of Hideshi (JP 2010199279 A), in view of Shimada (US 2009/0261861), in view of Ito et al. (US 2021/0048472 A1), and further in view of Sugiyama (US 2023/029087 A1), do not teach, suggest, or disclose all the limitations currently recited in independent claim 20, stating “None of the applied art relate to measuring the voltage difference between different sense positions on the same surface electrode…,” and “there would be no reason to apply the voltage difference measurement elements of Ito to devices such as the device in Nishimura.”
This argument has been fully considered but it is not persuasive, Examiner respectfully disagrees based on two reasonings. First, because the argument relies on an incorrect interpretation of the Ito prior art reference. In Ito, components 3 and 5 are not surface electrodes; rather, they are distinct conductor patterns located on the insulating substrate. Ito teaches that conductor pattern 3 is connected to the semiconductor die’s surface electrode 8 via bonding wire 10, and conductor pattern 5 is connected to the exact same surface electrode 8 via bonding wire 9, ([0020]-[0021], [0023], & [0027]). Therefore, Ito’s voltage sensing unit 12, which senses the potential difference between conductor pattern 3 and conductor pattern 5, is inherently capturing the potential difference between two distinct sensing positions (bonding points of wires 9 and 10) located on the same upper-surface electrode 8 ([0020]-[0021], [0028], [0030], [0046], [0050]-[0051], [0053]-[0054], [0058]-[0059], [0064], [0071], [0073], [0076], & [0080]). Since Ito teaches monitoring the potential difference between multiple connections on a single surface electrode to accurately detect wire deterioration without increasing the main current, it would have been obvious to a POSITA to apply this difference-output methodology to the multiple wiring positions on Nishimura’s single upper-surface source electrode 54. Therefore the rejection of independent claim 20 has been maintained, please see updated rejection below.
For the above stated reasoning, the rejections of independent claim 1, and dependent claims 3-10 & 17-19, which depend from and incorporate the limitations of amended independent claim 1, independent claim 11, and dependent claims 12-15, which depend from and incorporate the limitations of amended independent claim 11, and independent claim 20 are respectively maintained. Updated rejections based on amended features follow below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 9-10, & 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over by Nishimura (US 2017/0271452 A1, Pub. Date Sep. 21, 2017, hereinafter, Nishimura), in view of Shimada (US 2009/0261861 A1, Pub. Date Oct. 22, 2099, hereinafter, Shimada), and further in view of Ito et al. (US 2021/0048472 A1 Pub. Date Feb. 18, 2021, hereinafter, Ito).
Regarding independent claim 1, Nishimura, teaches:
A semiconductor device comprising (Fig. 1; [Abstract], [0006], [0033]-[0034], [0057], [0061] & [0100]):
a main element having an upper-surface electrode (Figs. 1 & 2; [0006], [0034]-[0036], [0057]-[0067] & [0100]: discloses the main element (MOSFET 90) and the upper-surface electrode (source electrode 54) is provided above the semiconductor substrate 10);
one or more output wiring lines that are connected to the upper-surface electrode (Fig. 1; [0034]-[0036], [0039]-[0040], [0042] & [0045]: source current wires 60 interpreted as one or more output wiring lines);
a first sense wiring line that is connected to a first sense position on the upper-surface electrode and that transmits potential at the first sense position (Figs. 1 & 2; [0006], [0034]-[0037], [0039]-[0040], [0042], & [0046]-[0047]: discloses the sense current wire 62 interpreted as first sense wiring line and the sense position is interpreted as the second region 50-2), wherein
the one or more output wiring lines include a first proximal wiring line having a shortest distance between its connection position to the upper-surface electrode and the first sense position (Fig. 1; [0037], [0039] & [0046]-[0047]: Fig. 1 illustrates multiple output wires (60-1, 60-2, 60-3, 60-4), source current wire 60-4 is physically the closest (proximal wiring line) located at a shortest distance to the sense current wire 62 connection in the 50-2 region (first sense region)),
the first proximal wiring line is connected to a first proximal position on the upper-surface electrode (Fig. 1; [0039] & [0046]-[0047]: shows source current wire 60-4 (first proximal wiring line) is connected to a location on the first region 50-2 of the source electrode 54 (upper-surface electrode) via solder 63, this connection point is the first proximal position), and
on the upper-surface electrode, a first inter-wiring line distance that is from the first sense position to the first proximal position is different from a half of a maximum distance that is from the first proximal position to an end of the upper-surface electrode (Fig. 1; [0037]-[0040]: the small distance between the connection point of wires (60-4 and 62) at the corner (the inter-wiring line distance) is structurally and visually distinct, different, and far from half of the maximum distance from 60-4 to the furthest opposite end (edge) of the source electrode 54);
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Nishimura, is silent in regard to:
a current sensing element through which current according to current flowing through the main element flows, the current sensing element having an output, wherein
the potential at the first sense position transmitted by the first sense wiring line is applied to a circuit portion between the current sensing element and a low potential terminal, and the output of the current sensing element is connected to the circuit portion between the current sensing element and the low potential terminal;
a sense ratio measurement unit that measures a sense ratio indicating a ratio of current flowing through the current sensing element to current outputted by the main element; and
However, Shimada, further teaches:
a current sensing element through which current according to current flowing through the main element flows, the current sensing element having an output (0044]-[0046]: sense MOSFET 2 acts as the current sensing element mirroring the main element power MOSFEET 1, outputting via its source terminal), wherein
the potential at the first sense position transmitted by the first sense wiring line is applied to a circuit portion between the current sensing element and a low potential terminal ([0004]-[0005], [0007], [0046]-[0048]: discloses the output routing where the potential is applied to a circuit portion (MOSFET 6 and differential amplifier 3), connected to a low potential terminal (measuring resistor 5/ground)); and the output of the current sensing element is connected to the circuit between the current sensing element and the low potential terminal ([0046]-[0048]);
a sense ratio measurement unit that measures a sense ratio indicating a ratio of current flowing through the current sensing element to current outputted by the main element ([0013], [0044] & [0052]: discloses measuring and maintaining the sense ratio representing the ratio of current between the main and sense elements via a differential amplifier); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Shimada’s current sensing architecture having an output with Nishimura’s device as a substitution of known techniques to improve similar devices, and to measure and utilize the sense ratio as taught by Shimada, according to known methods. Nishimura discloses the main and sense wiring on a semiconductor device, but does not detail a current sensing element through which current according to current flowing through the main element flows, having an output connected to a circuit portion between the current sensing element and a low potential terminal, wherein the potential at the first sense portion is applied to the circuit portion, and a sense ratio measurement unit that measures a sense ratio of the currents. Shimada teaches a current detection circuit including a sense MOSFET 2 serving as the current sensing element, an output connected to a measuring resistor 5 acting as the circuit portion toward a low potential terminal, and a differential amplifier 3 functioning as a sense ratio measurement unit to maintain a specific ratio of current between the sense and power MOSFETs ([0046]-[0048] & [0052]). The motivation for to incorporate Shimada’s sensing element and sense ratio measurement into Nishimura’s wiring configuration is to improve the accuracy of the current monitoring and detection while preventing excessive voltage from damaging the circuit components. By taking the ratio of the sense current to the main output current as taught by Shimada, the device can accurately monitor the proportional state of the device. This is a simple substitution of one known current measurement technique (absolute measurement) for another known, enhanced current measurement technique (ratio measurement) in the same field (semiconductor current sensing), ready for improvement, to yield the predictable variation (KSR) of a robust and accurate protectable current monitoring system utilizing the semiconductor device’s upper-surface electrode.
Nishimura, in combination with Shimada, are silent in regard to:
an electrode evaluation unit that evaluates the upper-surface electrode of the main element based on a deviation between an initial value of the sense ratio and the sense ratio measured by the sense ratio measurement unit, wherein the electrode evaluation unit determines that the upper-surface electrode has degraded if the deviation is equal to or greater than a reference value.
However, Ito, further teaches:
an electrode evaluation unit that evaluates the upper-surface electrode of the main element based on a deviation between an initial value of the sense ratio and the sense ratio measured by the sense ratio measurement unit ([0029] & [0078]-[0079]: teaches an evaluation unit (deterioration detection device 14) that calculates voltage ratios corresponding to inductance changes to evaluate the physical connection interface at the surface electrode, detects degradation at the surface electrode interface by monitoring the shift/deviation of an electrical ratio (applied to the sense ratio taught by Shimada) over time), wherein the electrode evaluation unit determines that the upper-surface electrode has degraded if the deviation is equal to or greater than a reference value ([0029] & [0041]-[0044]: discloses comparing the monitored voltage/ratio against a reference value to trigger a degradation at the surface electrode interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Ito’s degradation detection unit and logic into the combined Nishimura and Shimada device, by modifying the semiconductor device of Nishimura, which features sense and output wiring on an upper-surface electrode, further incorporating the sense ratio measurement of Shimada, according to known methods. The combination of Nishimura and Shimada lack an electrode evaluation unit that evaluates the upper-surface electrode of the main element based on a deviation between an initial value of the sense ratio and the sense ratio measured by the sense measurement unit, determining degradation if the deviation is equal to or greater than a reference value. Ito discloses a deterioration detection device 14 including a comparator 18 that compares a sensed voltage, representing a calculated ration, to a reference voltage to determine if a physical degradation, such as a crack near the interface of the surface electrode has occurred. The motivation to combine these teachings is to accurately detect and monitor the physical deterioration and health of the upper-surface electrode (such as detecting cracks or lift-off at the interface) without needing to inject/increase large test currents passing through the semiconductor or die. Furthermore, because the bonding wire and upper-surface electrode form a singular electrical and mechanical node, applying Ito’s ratio-based evaluation to the combined device results in a reliable system capable of continuously monitoring the structural integrity of the upper-surface electrode, improving the reliability and safety of the power semiconductor module, and yielding predictable results (KSR).
Regarding dependent claim 3, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034], [0057], [0061] & [0100]), wherein the first inter-wiring line distance is equal to or more than 0 times and equal to or less than 1/4 times the maximum distance (Figs. 1 & 4; [0037] -[0039]: Fig. 1 illustrates with an asymmetrical structure on a large square electrode 54, the sense connection (62 in 50-2) placed adjacent to the closest main output connection (60-4 in 50-1) in the corner of the chip, the close proximity makes the inter-wiring distance very small (Dprox-sense), the maximum distance (Dmax) is large and spans the majority of the chip’s surface to the farthest edge. Geometrically the distance between the two adjacent wires (first inter-wiring distance) is inherently greater than 0 but visible less than ¼ of the maximum distance spanning from that proximal wire to the far opposite edge of the source electrode 54).
Regarding dependent claim 7, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034]-[0036], [0039] [0057], [0061], [0078]-[0079] & [0100]), wherein when the upper-surface electrode (Fig. 1; [0034] & [0057]: source electrode 54 interpreted as the upper-surface electrode and illustrated in Fig. 1 the large rectangular pad) is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode (Fig. 1; [0036]-[0039]: first region 50-1 and second region 50-2 (contains the sense position, provided at the +x direction end and a +y direction end ) of source electrode 54, where proximal wire 60-4 (first proximal position) is adjacent to it, an equal division of the electrode by a straight line (e.g., a central horizonal line parallel to the x-side) places both adjacent positions in the same half region), the first sense position (Fig. 1; [0034] & [0036]-[0040]: connection point of the sense current wire 62 to the second region 50-2 of the source electrode) and the first proximal position (Fig. 1; [0036]-[0040]: connection point of a source current wire 60 to the first region 50-1 of the source electrode) are arranged in a same region (Fig. 1; [0034] & [0036]-[0040]: second region 50-2 is described and illustrated as being at a corner of the source electrode, the first region 50-1 constitutes the majority of the electrode, a connection point for source wire 60 in the area proximate to the corner and the sense wire 62 (first sense position) connection point would lie within the same quadrant if a line were drawn through the center of the electrode, either vertically or horizontally to divide it equally in half or into quadrants).
Regarding dependent claim 9, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0033]-[0036], [0039], [0057], [0061], [0078]-[0079] & [0100]), wherein when the upper-surface electrode (Figs. 1 & 2; [0034] & [0057]) is divided equally into a plurality of regions by a straight line that is parallel to a first side of the upper-surface electrode (Fig. 1; [0033]-[0034] & [0036]-[0039]: sides are parallel to the orthogonal x direction and y direction, therefore the required division lines parallel to the sides are possible) and also divided equally into a plurality of regions by a straight line that is parallel to a second side that is not parallel to the first side (Fig. 1; [0033]-[0034] & [0036]-[0039]), the first sense position (Fig. 1; 0034] & [0036]-[0040]: sense current wire to the second region 50-2 interpreted as the first sense position) and the first proximal position (Fig. 1; [0034], [0036]-[0038]: connection of the nearest source current wire 60 (60-4) to the first region 50-1 is interpreted as the first proximal position) are arranged in a same region (Fig. 1; [0034] & [0036]-[0040]: second region 50-2 (sense position) is provided at the +x direction end and a +y direction end of the source electrode 54, the proximal position 60-4 is adjacent to the sense position in the same corner, dividing the electrode into four equal quadrants places both adjacent positions in the same quadrant (same region)).
Regarding dependent claim 10, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079] & [0100]), wherein
the one or more output wiring lines include a second wiring line having a second-shortest distance between its connection position to the upper-surface electrode (Fig. 1; [0034], [0037]-[0040], & [0045]-[0047]: the source current wire 60-1 (bottom-left corner) is the second closest wire to the sense position 62 in the bottom-right corner) and the first sense position (Fig. 1; [0034] & [0039]: first sense position is the connection of the sense current wire 62 to the second region 50-2), and
a distance between the connection position of the second wiring line and the first sense position is longer than a distance between the first proximal position and the first sense position (Fig. 1; [0037]-[0040], & [0045]-[0047]: distance from the sense position 62 to the first proximal wire 60-4 is shorter because 60-4 is adjacent to the sense position 62, would be longer to either wire 60-1 or 60-3. Fig. 1 further illustrates the spatial distribution of the wires. The distance from the second wiring line (e.g., wire 60-1 or 60-3) to the sense wire 62 is visibly and proportionally longer than the distance from the first proximal wire 60-4 to the sense wire 62).
Regarding dependent claim 17, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0002], [0006], [0034], [0057], [0061] & [0100]), further comprising:
Nishimura, is silent in regard to:
an initial value storage unit that stores an initial value of the sense ratio, wherein the electrode evaluation unit compares a measured value with the initial value of the sense ratio.
However, Ito, further teaches:
an initial value storage unit that stores an initial value of the sense ratio ([0043]-[0044]: teaches using a built-in memory within a CPU to store an initially acquired voltage or reference value, the stored voltage corresponds to the baseline induction ratio of the wiring), wherein
the electrode evaluation unit compares a measured value with the initial value of the sense ratio ([0041]-[0044]: teaches that the evaluation unit (CPU/comparator) actively compares the newly measured, subsequent voltage values against the previously stored baseline reference voltage (the initial value) to evaluate whether physical degradation has occurred at the electrode connection).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the CPU and built-in memory evaluation functions taught by Ito into the combined Nishimura and Shimada device as a substitution of known techniques to improve similar devices. The combination of Nishimura and Shimada establishes the current sensing architecture but lacks an initial value storage unit that stores an initial value of the sense ratio and an electrode evaluation unit that compares a measured value with the stored initial value. Ito teaches a deterioration detection system that utilizes a CPU with a built-in memory acting as an initial value storage to record a previously acquired baseline reference voltage (initial value of the sense ratio), and subsequently compares newly measured values against the stored baseline to determine physical deterioration. The motivation for this combination is to provide a reliable, historical baseline comparison to accurately track the gradual degradation of the device’s physical connections over time, thereby improving the long-term diagnostic accuracy of the current sensing system ([0043]-[0044]). This predictable variation predictably yields a semiconductor device capable of archiving its optimal initial operating state and detecting structural failures by calculating deviations from the securely stored baseline, yielding achievable results and a predictable improved current sensing accuracy in a known semiconductor device layout (KSR).
Regarding dependent claim 18, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0002], [0006], [0034], [0057], [0061] & [0100]), further comprising:
a control unit that controls current to be flowed through the main element (Fig. 4; [0074]-[0077] & [0100]: control section 98 (control unit) controls the gate potential VG of the MOSFET 90 (main element to increase or decrease the main current)) based on the sense ratio measured by the sense ratio measurement unit ([0052] & [0074]-[0077]: current value used by the control section 98 is obtained by measuring the sense current and multiplying by the present sense ratio, the measured current value is the basis for the control decision, and actively controls the main current flowing through the main element (MOSFET 90) by adjusting the gate potential).
Regarding dependent claim 19, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034], [0057], [0061] & [0100]), further comprising:
Nishimura, is silent in regard to:
a sense resistor that is arranged between the current sensing element and a reference potential, wherein
a resistance value of the sense resistor is variable.
However, Shimada, further teaches:
a sense resistor that is arranged between the current sensing element and a reference potential ([0046]-[0047]: details a sensing leg comprising a variable resistance device (MOSFET 6) and a measuring resistor 5, routed between the current sensing element (sense MOSFET 2) and a fixed reference potential (ground)), wherein
a resistance value of the sense resistor is variable ([0015], [0020], [0046]-[0047], [0052], [Claim 1], [Claim 6], [Claim 14], [Claim 15], [Claim 16], & [Claim 17]: defines MOSFET 6 as a “variable resistance device” and describes how its resistance value is dynamically increased or decreased by the differential amplifier 3 to balance the circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shimada’s variable resistance device into the sensing path of Nishimura’s combined device as a substitution of known techniques to improve similar devices. Nishimura discloses a semiconductor device with a main element and sense routing but fails to detail a sensor resistor arranged between the current sensing element and a reference potential, wherein a resistance value of the sense resistor is variable. Shimada teaches a current detection circuit incorporating a variable resistance device (MOSFET 6) and a measuring resistor (5) arranged between the sense MOSFET (2) and a fixed ground potential, where the resistance value of the MOSFET 6 dynamically changes based on the amplifier’s output. The motivation for this implementing this variable sense resistor is to dynamically adjust the resistance in the path to maintain equal drain-source voltages between the main and sense elements, improving the accuracy of the current detection ([0007] & [0052]). This combination predictably yields an optimized current sensing circuit capable of accurate load monitoring without risking electrostatic breakdown (KSR).
Claims 4-6 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Shimada, in view of Ito, and further in view of Hideshi (JP 2010199279 A, Pub. Date Sep. 09, 2010, hereinafter, Hideshi).
Regarding dependent claim 4, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034]-[0036], [0039] [0057], [0061], [0078]-[0079] & [0100]),
Nishimura, is silent in regard to:
wherein the first inter-wiring line distance is equal to or more than 3/4 times and equal to or less than 1 times the maximum distance.
However, Hideshi, further teaches:
wherein the first inter-wiring line distance is equal to or more than 3/4 times and equal to or less than 1 times the maximum distance (Figs. 1 & 10; [Pgs. 1-2, Solution paragraph], [0002]-[0003], [0005], [0007]-[0012], [0026], & [0032]: teaches that the Kelvin wiring 86a is connected to “an end side part 86 farthest from a position 85b where the main wiring 85a is connected, specifies this configuration makes the distance between the connection points long, utilizing the electrode’s resistance to influence the sense circuit, and connecting to the “farthest” point results in a distance that is Iess than 1 times the maximum possible distance on that electrode, falls within the claimed range of ¾ to 1 times. Further, teaches placing the proximal main wire 85a on the edge of the pard and the sense wire 86a on the far opposite edge, this layout maximizes the distance between the two connections across the entire pad, making the inter-wiring distance 100% (1 times) the maximum distance from the proximal wire to the pad edge, satisfying the ¾ to 1 times ratio).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wire spacing in Nishimura by implementing the maximized distance arrangement taught by Hideshi, incorporating the first inter-wiring line distance is equal to or more than 3/4 times and equal to or less than 1 times the maximum distance, as a substitution of known techniques to improve similar devices. Nishimura discloses the base semiconductor device with source and sense wiring but does not detail the first inter-wiring distance being equal to one or more than ¾ times and equal to or less than 1 times the maximum distance. Hideshi teaches a semiconductor device wiring layout where the sense wiring (Kelvin wiring 86a) is placed at a position farthest away from the main wiring (85a), sch as on the opposite edge of the electrode pad, maximizing the inter-wiring distance to be substantially equal to 1 times the maximum distance across the pad. Alternatively attainable, by modifying the semiconductor device of Nishimura by applying the teachings of Hideshi, to configure the device such that the sense current wire 62 is connected to the front surface electrode 54 at a position that is the farthest from the connection point of the source current wires 60 of Nishimura, achieving a first inter-wiring line distance that is equal to or more than ¾ times and equal to or less than 1 times the maximum distance. The motivation for this combination is to intentionally increase the resistance component of the electrode pad between the main and sense wiring connections to suppress temperature-dependent fluctuations in the current sense ratio ([0008]-[0009]). This combination results in a predictable variation of the electrode layout that improves the stability and accuracy of the current sensing functions across varying operating temperatures, as taught by Hideshi (KSR).
Regarding dependent claim 5, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034]-[0036], [0039] [0057], [0061], [0078]-[0079] & [0100]),
Nishimura, is silent in regard to:
wherein the upper-surface electrode has a rectangular shape having a shorter side in a first direction and a longer side in a second direction, and
the first sense position and the first proximal position are arranged side-by-side in the first direction.
However, Hideshi, further teaches:
wherein the upper-surface electrode has a rectangular shape (Fig. 3; [0020: source pad 85 is formed on the main source electrode 81, interpreted as the upper-surface electrode) having a shorter side in a first direction and a longer side in a second direction (Fig. 3; [0020]: the plan view of the source pad 85 is explicitly depicted as a rectangle with a shorter side and a longer side, defining the first and second directions), and
the first sense position and the first proximal position are arranged side-by-side in the first direction (Fig. 3; [0008], [0020] & [0029]: describes the Kelvin terminal (sense position) being provided at a corner of the rectangular pad, Fig. 3 further illustrates the Kelvin terminal 86 at a corner, when the main terminal 85b is at the center, placing the sense terminal at a corner results in them being arranged along both the shorter and longer sides).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the upper-surface electrode having a rectangular shape having a shorter side in a first direction and a longer side in a second direction, and the first sense position and the first proximal position are arranged side-by-side in the first direction, of Hideshi to Nishimura, in order to attain, by modifying the semiconductor device of Nishimura by applying the teachings of Hideshi, knowing that the terminals can be located anywhere on the periphery, to optimize the temperature stability of the current sensing function in Nishimura’s device, a POSITA would be motivated to position the sense connection (62, 50-2) at a location on the rectangular electrode that is farthest from the main current connection (60, 50-1) of Nishimura, and in the rectangular layout of Nishimura’s electrode 54, one of the “farthest points” is a location along the shorter side (x-direction), and this geometric property of a rectangle is illustrated by Hideshi’s Fig. 3, where the simple and predictable optimization would result in the first sense position and the first proximal position arranged side-by-side in the first (shorter-side) direction (y-direction) as claimed, and would result in a predictable (common design variation) and known optimization (maximizing connection point distance for stability) in a known semiconductor device layout field (KSR).
Regarding dependent claim 6, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034]-[0036], [0039] [0057], [0061], [0078]-[0079] & [0100]),
Nishimura, is silent in regard to:
wherein when the upper-surface electrode is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode, the first sense position is arranged in a first region and the first proximal position is arranged in a second region.
However, Hideshi, further teaches:
wherein when the upper-surface electrode (Figs. 1, 3, & 10; [0002], [0007], [0016], [0020], & [0032]: source pad 85 is formed on the main source electrode 81) is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode (Figs. 1, 3, & 10; [0002], [0007]-[0009], [0016], [0020], [0026], & [0032]: since the main terminal portion 85b is located at the center of the source pad 85, the Kelvin terminal portion 86 is formed at a position farthest from the terminal portion 85b), the first sense position is arranged in a first region (Figs. 1, 3, & 10; [0007] & [0020]: Kelvin wiring 86a is connected to the Kevin terminal portion 86) and the first proximal position (Figs. 1, 3, & 10; [0007], [0020], & [0032]: main wiring 85a is connected to the main terminal portion 85b) is arranged in a second region (Figs. 1, 3, & 10; [0007]-[0009], [0020], [0026], & [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the grouped wire spacing in Nishimura by implementing the separated, opposite-edge distance arrangement taught by Hideshi. Nishimura discloses the semiconductor device with a front upper-surface electrode 54 having a first region 50-1 for a main terminal connection and a spatially distinct second region 50-2 for a sense terminal connection, but fails to detail the arrangement where dividing the electrode equally by a straight line parallel to any side places the first sense position in a first region and the first proximal position in a second region. Hideshi teaches a semiconductor wiring layout that places the main wiring 85a at one edge of the source pad and the Kelvin wiring 86a at the opposite edge 127, such that bisecting the pad parallel to these edges inherently separates the connection positions into two distinct regions (Fig. 10; [0032]). Alternatively attainable, by modifying the semiconductor device of Nishimura to have the first and second connection regions by applying the teachings of Hideshi, Nishimura provides the semiconductor device with a front surface electrode 54, Hideshi teaches the benefit of spatially separating the main terminal connection 85b and the sense (Kelvin) terminal connection 86 on a single electrode 85, and instructs that placing the sense connection at a position farthest from the main connection (e.g., center vs. corner), helps to incorporate the electrode’s resistance, which stabilizes the current sense ratio against temperature fluctuations ([0008] & [0029]). A POSITA seeking to optimize Nishimura’s device, would have been motivated by Hideshi’s teachings to position Nishimura’s sense connection point in the second region 50-2 and the main connection point in the first region 50-1, so that they are located in different, distinctly separated regions of the front surface electrode (e.g., placing one near a center and the other near a peripheral edge). Further, the motivation for combination is intentionally increase the resistance component of the electrode pad between the main and sense wiring connections to suppress temperature-dependent fluctuations in the current sense ratio ([0008]-[0009]). This combination yields the predictable variation of an optimized electrode layout that guarantees a predictable improved current sensing accuracy and known optimization (maximizing connection point distance for stability) and current sensing across varying operating temperatures by physically isolating the sense and proximal positions into separate regions (KSR).
Regarding dependent claim 8, Nishimura, teaches:
The semiconductor device according to claim 1 (Fig. 1; [Abstract], [0006], [0034]-[0036], [0039] [0057], [0061], [0078]-[0079] & [0100]), wherein when the upper-surface electrode is divided equally into a plurality of regions by a straight line that is parallel to a first side of the upper-surface electrode (Fig. 1; [0034] & [0037]: establishes a substantially rectangular upper-surface electrode pad (source electrode 54) defined by orthogonal x and y directions, bisecting the electrode pad with orthogonal straight lines parallel to its sides established four equal quadrant regions) and also divided equally into a plurality of regions by a straight line that is parallel to a second side that is not parallel to the first side (Fig. 1; [0034] & [0037]: Fig. 1 illustrates the source electrode 54 is a contiguous, substantially rectangular pad, whose sides define natural axes for division),
Nishimura, is silent in regard to:
the first sense position is arranged in a first region and the first proximal position is arranged in a second region that is provided diagonally opposite to the first region.
However, Hideshi, further teaches:
the first sense position is arranged in a first region (Figs. 3 & 10; [0020] & [032]: Kelvin terminal portion 86 is a sense terminal in a first region) and the first proximal position is arranged in a second region (Figs. 3 & 10; [0020] & [0032]: main terminal portion 85b is the primary current-carrying (proximal) terminal) that is provided diagonally opposite to the first region (Figs. 3 & 10; [0020] & [0032]: Fig. 3 illustrates the main terminal 85b in the center and the Kelvin terminal 86 in a corner, these two points are diagonally opposite on the rectangular pad, and Kelvin terminal 86 is spatially separated from the main current pads 87).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wire spacing in Nishimura by arranging the proximal main wire and the sense wire diagonally opposite quadrants as taught by Hideshi as a substitution of known techniques to improve similar devices. By modifying the semiconductor device featuring an front upper-surface electrode 54 of Nishimura containing both main source wiring (a proximal/main current position (60/50-1) and a sense position (62/50-2), but fails to teach the specific arrangement where bisecting the electrode into quadrants places the first sense position and the first proximal position in diagonally opposite regions. Hideshi teaches this specific wiring layout of placing the sense terminal 86 and the main terminal 85b in diagonally opposite regions (center and corner) of a rectangular upper-surface electrode to intentionally maximize the distance between the main wiring and the Kelvin sense wiring (alternatively Fig. 10 main wiring 85a and Kelvin wiring 86a) by placing the sense wiring at the corner of the edge furthest away from the main wiring connection. The motivation for this combination is to increase the resistance component of the electrode pad between the main and sense connections to suppress temperature-dependent fluctuations in the current sense ratio, and ensure accurate and stable measurements ([0008] & [0029]). This combination yields the predictable variation of an optimized electrode layout that provides consistent current sensing across varying operating temperatures by isolating the sense connection point in a corner region and proximal positions into maximally distant, diagonally opposite regions (KSR).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Shimada, and further in view of Sugiyama et al (US 2023/0290871 A1, Fil. Date Sep. 12, 2022, hereinafter, Sugiyama).
Regarding independent claim 11, Nishimura, teaches:
A semiconductor device comprising (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079], & [0100]):
a main element having an upper-surface electrode (Figs. 1 & 2; [0006], [0034]-[0036], [0057]-[0067] & [0100]: discloses the main element (MOSFET 90) and the upper-surface electrode (source electrode 54) is provided above the semiconductor substrate 10);
one or more output wiring lines that are connected to the upper-surface electrode (Fig. 1; [0034]-[0036], [0039]-[0040], [0042], & [0045]: source current wires 60 interpreted as one or more output wiring lines);
a first sense wiring line that is connected to a first sense position on the upper-surface electrode and that transmits potential at the first sense position (Figs. 1 & 2; [0006], [0034], [0036]-[0037], [0039]-[0040], [0042], & [0046]-[0047]: discloses the sense current wire 62 interpreted as first sense wiring line and the sense position is interpreted as the second region 50-2), wherein
the one or more output wiring lines include a first proximal wiring line having a shortest distance between its connection position to the upper-surface electrode and the first sense position (Fig. 1; [0037], [0039] & [0046]-[0047]: Fig. 1 illustrates multiple output wires (60-1, 60-2, 60-3, 60-4), source current wire 60-4 is physically the closest (proximal wiring line) located at a shortest distance to the sense current wire 62 connection in the 50-2 region (first sense region)),
the first proximal wiring line is connected to a first proximal position on the upper-surface electrode (Fig. 1; [0039] & [0046]-[0047]: shows source current wire 60-4 (first proximal wiring line) is connected to a location on the first region 50-2 of the source electrode 54 (upper-surface electrode) via solder 63, this connection point is the first proximal position), and
on the upper-surface electrode, a first inter-wiring line distance that is from the first sense position to the first proximal position is different from a half of a maximum distance that is from the first proximal position to an end of the upper-surface electrode (Fig. 1; [0037]-[0040]: the small distance between the connection point of wires (60-4 and 62) at the corner (the inter-wiring line distance) is structurally and visually distinct, different, and far from half of the maximum distance from 60-4 to the furthest opposite end (edge) of the source electrode 54);
Nishimura, is silent in regard to:
a current sensing element through which current according to current flowing through the main element flows, the current sensing element having an output, wherein
the potential at the first sense position transmitted by the first sense wiring line is applied to a circuit portion between the current sensing element and a ground potential, and the output of the current sensing element is connected to the circuit portion between the current sensing element and the ground potential; and
However, Shimada, further teaches:
a current sensing element through which current according to current flowing through the main element flows, the current sensing element having an output (0044]-[0046]: sense MOSFET 2 acts as the current sensing element mirroring the main element power MOSFEET 1, outputting via its source terminal), wherein
the potential at the first sense position transmitted by the first sense wiring line is applied to a circuit portion between the current sensing element and a ground potential ([0004]-[0005], [0007], & [0046]-[0048]: the potential from the first sense position is applied to the differential amplifier 3, which controls the circuit portion (MOSFET 6), the sense MOSFET 2 outputs to MOSFET 6, which is arranged between the sense element and a grounded measuring resistor 5), and the output of the current sensing element is connected to the circuit portion between the current sensing element and the ground potential ([0046]-[0048]); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Shimada’s current sensing circuit architecture with Nishimura’s physical electrode wiring layout as a substitution of known techniques. Nishimura discloses the main semiconductor element and upper-surface sense wiring, but does not detail a current sensing element having an output, where the potential at the first sense position is applied to a circuit portion located between the current sensing element and a ground potential. Shimada teaches a current detection circuit comprising a sense MOSFET 2 as the current sensing element, where the main element’s source potential is applied to an operational amplifier that controls a variable resister (MOSFET 6) located between the sense element and a grounded measuring resistor 5 ([0046]-[0048]). A POSITA would be motivated to incorporate this specific sensing circuit to actively monitor the load current and regulate voltage differences to prevent excessive voltage from damaging the inputs of the differential amplifier ([0052]), processing the sense potential extracted by Nishimura’s optimized wiring layout. Integrating Shimada’s external evaluation circuit (e.g., differential amplifier) provides a mechanism to utilize the extracted potential for overcurrent protection and current monitoring. This combination, according to known methods yields the predictable variation of a safe, accurate current detection system integrated directly with the device’s upper-surface electrode wiring (KSR).
Nishimura, in combination Shimada, are silent in regard to:
a second sense wiring line that is connected to a second sense position on the upper-surface electrode and that is for applying potential at the second sense position to the circuit portion between the current sensing element and the ground potential, wherein on the upper-surface electrode, a second inter-wiring line distance that is from the second sense position to the first proximal position is different from the first inter-wiring line distance.
However, Sugiyama, further teaches:
a second sense wiring line that is connected to a second sense position on the upper-surface electrode and that is for applying potential at the second sense position to the circuit portion between the current sensing element and the ground potential (Fig. 4; [0029]-[0031] & [0040]-[0041]: teaches routing a second sense wiring line (second Kelvin terminal 47) from a second sense position (Kelvin source 43) to serve as the ground potential reference for the sense current monitor loop), wherein on the upper-surface electrode, a second inter-wiring line distance that is from the second sense position to the first proximal position is different from the first inter-wiring line distance (Figs. 1 & 4; [0029]-[0031] & [0040]-[0041]: since the first and second positions (first and second Kelvin source terminals) are placed at different physical locations along the y-axis, their inter-wiring distances to the proximal main output line differ, distributed widely both on the periphery and interspersed centrally, their physical distances to the initial proximal output wire naturally vary).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined Nishimura and Shimada semiconductor device of Nishimura and Shimada by incorporating Sugiyama’s second sense wiring line to ground the sensing circuit portion, representing a predictable variation of known techniques to improve similar devices, where multiple sense wiring lines connected to distinct second sense positions with varying inter-wiring distances. The combination of Nishimura and Shimada lack a second sense wiring line connected to a second sense position on the upper-electrode surface for applying potential to the circuit portion between the sensing element and ground, wherein the second inter-wiring line distance differs from the first. Sugiyama discloses providing multiple sense connections on a source electrode, specifically teaching a first Kelvin source terminal 45 for a gate loop and a second Kelvin source terminal 47 for a sense current monitor loop L2 connected to a ground terminal, which are physically located at different distances from the main source elements. A POSITA would be motivated to isolate the sensing ground via the second sense wiring line to shield micro sense voltages from gate control signals, monitoring variations in current distribution across the upper-surface electrode, thereby improving the accuracy and stability of the sense current monitoring control ([0039]). Implementing this dual-sense wiring layout predictably results in a semiconductor device free from cross-loop interference between the power control and current sensing circuits. Relying on a single sense position can lead to blind spots where overcurrent or “hot spots” can cause device failure before the single sense terminal detects a fault. Further, adopting Sugiyama’s distributed sense positions, the evaluation circuit can monitor multiple areas of the die simultaneously. This yields the predictable result (KSR) of enhanced device reliability and robust fault protection, preventing thermal runaway or current overloading.
Claims 12 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Shimada, in view of Sugiyama, and further in view of Hideshi.
Regarding dependent claim 12, Nishimura, teaches:
The semiconductor device according to claim 11 (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079], & [0100]), wherein when the upper-surface electrode (Figs. 1 & 2; [0006], [0034], [0057]-[0067] & [0100]) is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode (Fig. 1; [0035]-[0040]: first region 50-1 and second region 50-2 are distinct areas of electrode 54, a straight line can divide them), the first sense position is arranged in a first region (Fig. 1; [0035]-[0040]: source current wires 60 connected to the first region 50-1) and the second sense position is arranged in a second region (Fig. 1; [0035]-[0040]: second current wire 62 connected to second region 50-2).
Nishimura, is silent in regard to:
wherein when the upper-surface electrode is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode, the first sense position is arranged in a first region and the second sense position is arranged in a second region.
However, Hideshi, further teaches:
The Examiner is combining Hideshi in view of Sugiyama by implementing the presence of a first and second sense position on the electrode pad of Sugiyama ([0029]-[0030] & [0039]), combined disclose modifying the wiring layout to place distinct functional connections on opposite edges, isolating them into different regions upon bisection.
wherein when the upper-surface electrode is divided equally into a plurality of regions by a straight line that is parallel to any side of the upper-surface electrode, the first sense position is arranged in a first region and the second sense position is arranged in a second region (Fig. 10; [0032]: teaches maximizing the physical distance between critical connections by placing them on opposite edges of the pad. Applying this geometric distancing to Sugiyama’s dual sense positions forces the first sense position into one half of the pad (first region) and the second sense position into the opposite half (second region) when the pad is bisected).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device by separating the first sense position and the second sense position into distinct regions, as taught by Hideshi, as a predictable variation of known techniques to improve similar devices. The combination of Nishimura, Shimada, and Sugiyama discloses a semiconductor device having an upper-surface electrode with a first sense position and a second sense position, but fails to teach that when the electrode is divided equally by a straight line parallel to any side, the first sense position is arranged in a first region and the second sense position is arranged in a second region. Hideshi teaches an optimized semiconductor wiring layout that intentionally maximizes the distance between different functional connections by placing them on far opposite edges of the electrode pad, such that bisecting the pad inherently separates them into distinct geometric regions (Fig. 10; [0032]). The motivation for this combination is to increase the distance between the separate sense connections to prevent localized thermal coupling and electrical cross-loop interference between the gate control loop and the current monitor loop ([Hideshi: 0008]-[0009]; Sugiyama: [0039]). This predictable variation yields an optimized electrode layout that provides a stable, accurate current sensing and gate control across varying operating temperatures by physically isolating the two sense positions into separate regions (KSR).
Regarding dependent claim 14, Nishimura, teaches:
The semiconductor device according to claim 12 (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079] & [0100]), further comprising:
Nishimura, is silent in regard to:
a first sense terminal that outputs potential at the first sense position to outside of the semiconductor device;
a second sense terminal that outputs potential at the second sense position to outside of the semiconductor device.
However, Sugiyama, further teaches:
a first sense terminal that outputs potential at the first sense position to outside of the semiconductor device ([0025]-[0031]: teaches a first sense terminal (first Kelvin source terminal 45) that transmits the potential of the first sense position directly to the outside of the semiconductor device (the first ship 10A), routing it to an external gate driver (second chip 20));
a second sense terminal that outputs potential at the second sense position to outside of the semiconductor device ([0029]-[0031]: teaches a second sense terminal (second Kelvin source terminal 47) that transmits the potential of the second sense position to the outside of the semiconductor device (first chip 10 A), routing it to the external gate driver (second chip 20)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the first and second external sense output terminals taught by Sugiyama into the combined Nishimura device as a substitution of known techniques to improve similar devices. The combination of Nishimura and the previously established references lack a first sense terminal that outputs potential at the first sense position to the outside of the semiconductor device and a second sense terminal that outputs potential at the second sense position to the outside of the semiconductor device. Sugiyama discloses a semiconductor device (first chip 10 A) featuring a first sense terminal (first Kelvin source terminal 45) and a second sense terminal (second Kelvin source terminal 47) that output their respective potentials to a separate gate driver chip 20 ([0029]-[0031]). The motivation for implementing these multiple external sense terminals is to allow separate, isolated routing of the sense potentials to an external driver chip, thereby shielding micro sense with sense voltages from gate control signals to improve the monitor control of the sense current ([0039]). This combination predictably yields an optimized current detection system capable of reliably exporting dual sense potentials to external control circuitry without suffering from close-loop signal interference (KSR).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Shimada, in view of Sugiyama, in view of Hideshi, and further in view of Fukuhara (US 2022/0029410 A1, Pub. Date Jan.27, 2022, hereinafter, Fukuhara).
Regarding dependent claim 13, Nishimura, teaches:
The semiconductor device according to claim 12 (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079] & [0100]), further comprising:
Nishimura, is silent in regard to:
a selector that selects either potential at the first sense position or potential at the second sense position, and applies it to the circuit portion between the current sensing element and the ground potential.
However, Fukuhara, further teaches:
a selector that selects either potential at the first sense position or potential at the second sense position (Fig. 1; [0044], [0052], & [0054]: teaches a selector mechanism comprising multiple switch elements (18, 28) configured to actively select whether a first source voltage (potential at a first position) or a second source voltage (potential at a second position) is passed forward), and applies it to the circuit portion between the current sensing element and the ground potential ([0054], [0057], [0074], & [0077]: teaches that the selector (elements 18, 28) applies the selected potential directly to the shared operational amplifier 40, the op-amp represents the circuit portion controlling the connection between the current sensing element and ground).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the selector switches taught by Fukuhara into the combined device’s sensing architecture taught by Nishimura/Sugiyama, according to known methods, as a predictable variation. The combination of Nishimura, Shimada, and Sugiyama discloses a semiconductor device with multiple sense positions and a current sensing circuit but fails to teach a selector that selects either the potential at the first sense position or the second sense position and applies it to the circuit portion between the current sensing element and ground. Fukuhara discloses a current sense circuit comprising a selector (drive-side elements 19, 28 and detect-side elements 19, 29) that selectively switches between multiple channels to input either a first source potential or a second source potential to a shared operational amplifier 40. A POSITA would be motivated for this combination to allow a single, shared operational amplifier circuit to selectively monitor multiple different sense positions on the chip, thereby reducing the physical size and manufacturing cost of the current detection circuit by eliminating the need for redundant amplifiers ([0077]-[0078]). Applying this known technique to improve similar devices predictably results in an efficient, compact semiconductor device capable of safely multiplexing multiple sense potentials into a monitoring circuit without cross-channel signal interference, reducing the overall component count, lowering manufacturing costs, and minimizing the physical size of the evaluation circuitry while retaining a robust, multi-point die monitoring (KSR).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Shimada, in view of Sugiyama, in view of Hideshi, and further in view of Zhou et al. (US 2023/0417604 A1, Fil. Date Jun. 24, 2022, hereinafter, Zhou).
Regarding dependent claim 15, Nishimura, teaches:
The semiconductor device according to claim 14 (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079] & [0100]), further comprising:
Nishimura, is silent in regard to:
a third sense wiring line that is connected to a third sense position between the first sense position and the second sense position on the upper-surface electrode; and
a third sense terminal that outputs potential at the third sense position to outside of the semiconductor device.
However, Zhou, further teaches:
a third sense wiring line that is connected to a third sense position between the first sense position and the second sense position on the upper-surface electrode (Fig. 2; [0037]-[0039]: teaches a spatial arrangement on a single continuous electrode where a specific sense terminal (GK1, acting as the third sense position) is positioned physically between an outer first terminal (Gf1) and another terminal (Gk2) along the length of the electrode); and
a third sense terminal that outputs potential at the third sense position to outside of the semiconductor device (Fig. 2; [Abstract], [0006], [0010], [0012], [0026]-[0029], [0035], [00037]-[0039], [0043], [Claim 1], [Claim 3], [Claim 4], [Claim 5], [Claim 7], [Claim 8], [Claim 9], [Claim 10], [Claim 12], [Claim 15], & [Claim 17]: teaches that this intermediate terminal (GK1) outputs its localized potential to the outside of the semiconductor device by electrically connecting to an external Kelvin sensor apparatus or measurement device to determine localized resistance and heating effects).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the third sense wiring line and terminal arrangement taught by Zhou into the upper-surface electrode of the combined device as a predictable variation. The combination of Nishimura, Shimada, Sugiyama, and Hideshi lacks a third sense wiring line connected to a third sense position located between the first and second sense positions on the upper-surface electrode, and a third sense terminal that outputs this potential to the outside of the device. Zhou discloses a semiconductor device utilizing a multi-terminal Kelvin sensor configuration on a single continuous electrode, teaching an intermediate sense terminal connection (GK1) physically positioned between other outer terminals (Gf1 and GK2) that outputs its localized potential to an outside measurement device. The motivation for placing this third sense terminal physically between the other connections is to enable accurate, localized multi-terminal Kelvin measurements across specific segments of the electrode by isolating the voltage reading from contact resistance voltage drops occurring at the outer terminals ([0035] & [0038]). This substitution of known techniques to improve similar devices predictably yields an optimized external terminal layout that ensures precise, interference-free transmission of localized sense potentials to external monitoring circuitry (KSR).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, in view of Sugiyama, and further in view of Ito.
Regarding independent claim 20, Nishimura, teaches:
A semiconductor device comprising (Fig. 1; [Abstract], [0006], [0033]-[0040], [0057], [0061], [0078]-[0079], & [0100]):
a main element having an upper-surface electrode (Figs. 1 & 2; [0006], [0034]-[0036], [0057]-[0067] & [0100]: discloses the main element (MOSFET 90) and the upper-surface electrode (source electrode 54) is provided above the semiconductor substrate 10);
one or more output wiring lines that are connected to the upper-surface electrode (Fig. 1; [0034]-[0036], [0039]-[0040], [0042], & [0045]: source current wires 60 interpreted as one or more output wiring lines);
a first sense wiring line that is connected to a first sense position on the upper-surface electrode and that transmits potential at the first sense position (Figs. 1 & 2; [0006], [0034], [0036]-[0037], [0039]-[0040], [0042], & [0046]-[0047]: discloses the sense current wire 62 interpreted as first sense wiring line and the sense position is interpreted as the second region 50-2, to transmit the electrode’s potential), wherein
the one or more output wiring lines include a first proximal wiring line having a shortest distance between its connection position to the upper-surface electrode and the first sense position (Fig. 1; [0037], [0039] & [0046]-[0047]: Fig. 1 illustrates multiple output wires (60-1, 60-2, 60-3, 60-4), source current wire 60-4 is physically the closest (proximal wiring line) located at a shortest distance to the sense current wire 62 connection in the 50-2 region (first sense region)),
the first proximal wiring line is connected to a first proximal position on the upper-surface electrode (Fig. 1; [0039] & [0046]-[0047]: shows source current wire 60-4 (first proximal wiring line) is connected to a location on the first region 50-2 of the source electrode 54 (upper-surface electrode) via solder 63, this connection point is the first proximal position), and
on the upper-surface electrode, a first inter-wiring line distance that is from the first sense position to the first proximal position is different from a half of a maximum distance that is from the first proximal position to an end of the upper-surface electrode (Fig. 1; [0037]-[0040]: the small distance between the connection point of wires (60-4 and 62) at the corner (the inter-wiring line distance) is structurally and visually distinct, different, and far from half of the maximum distance from 60-4 to the furthest opposite end (edge) of the source electrode 54);
Nishimura, is silent in regard to:
a second sense wiring line that is connected to a second sense position on the upper-surface electrode and that transmits potential at the second sense position; and
However, Sugiyama, further teaches:
a second sense wiring line that is connected to a second sense position on the upper-surface electrode and that transmits potential at the second sense position (Fig. 4; [0025]-[0031] & [0040]-[0041]: teaches routing a second sense wiring line (second Kelvin terminal 47) from a second sense position (Kelvin source 43) to transmit a second sense potential); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nishimura’s wiring configuration to include the second sense wiring line and second sense position as taught by Sugiyama, representing a substitution of known techniques to improve similar devices. Nishimura discloses a semiconductor device with a first sense wiring line but lacks a second wiring line that is connected to a second sense position on the upper-surface electrode and that transmits potential at the second sense position. Sugiyama discloses a semiconductor device featuring multiple sense-related connections, specifically teaching a second sense wiring line, designated as the second Kelvin source terminal 47, that connects to a distinct Kelvin source part 43 acting as the second sense wiring line and second sense position on the electrode surface ([0026] & [0030]). The motivation for incorporating this second sense wiring line is to enable monitoring of a localized voltage drop across a specific sense resistance region on the chip, allowing for overcurrent detection without interfering with the main power lines ([0032]). This combination predictably results in a reliable semiconductor layout capable of safely transmitting multiple isolated sense potentials for advanced monitoring (KSR).
Nishimura, in combination with Sugiyama, are silent in regard to:
a difference output portion that outputs a difference between potential at the first sense position and potential at the second sense position.
However, Ito, further teaches:
a difference output portion that outputs a difference between potential at the first sense position and potential at the second sense position ([Abstract], [0008]-[0009], & [0020]-[0021]: discloses a voltage sensing unit 12 that functions as a difference output portion by detecting and outputting the potential difference between two distinct sensing points on the semiconductor package).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Ito’s difference output portion into the combined Nishimura and Sugiyama device as a predictable variation, by incorporating a second sense wiring line connected to a second sense position and a difference output portion, as taught by Ito, and according to known methods. The combination of Nishimura and Sugiyama provides multiple sense positions but does not detail a difference output portion that outputs a difference between potential at the first sense position and potential at the second sense position. Ito discloses a voltage sensing unit 12 serving as a difference output portion that connects to multiple conductor patterns to sense and output the potential difference between those respective positions during device operation ([0020]-[0021]). A POSITA would have been motivated to make this combination of adding the difference output portion to accurately detect and output the potential difference between two sense lines to determine physical deterioration or current anomalies within the device package without requiring a damaging increase in the main operating current ([0008]-[0009]). By measuring the differential potential between two distinct points on the upper-surface electrode rather than relying on a single measurement, the modified device would be able to cancel out common-mode noise, compensate parasitic voltage drops across the source electrode, and detect localized variations or degradation within the device package, yielding a robust controlled power module. Applying this known technique to improve similar devices yields a comprehensive monitoring system that safely and continuously evaluates the critical potential difference between the isolated sense positions (KSR).
Conclusion
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/HUGO NAVARRO/ Examiner, Art Unit 2858 August 19, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 8/28/2026
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